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Intel
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IXP42X product line and IXC1100 control plane processors—Intel XScale
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Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
50 Order Number: 252480-006US
Note: If exceptions are allowed to occur in the middle of this routine, the TLB may end up
caching a translation that is about to be locked. For example, if R1 is the virtual
address of an interrupt service routine and that interrupt occurs immediately after the
TLB has been invalidated, the lock operation will be ignored when the interrupt service
routine returns back to this code sequence. Software should disable interrupts (FIQ or
IRQ) in this case.
As a general rule, software should avoid locking in all other exception types.
The proper procedure for locking entries into the data TLB is shown in Example 3 on
page 51.
Example 2. Locking Entries into the Instruction TLB
; R1, R2 and R3 contain the virtual addresses to translate and lock into
; the instruction TLB.
; The value in R0 is ignored in the following instruction.
; Hardware guarantees that accesses to CP15 occur in program order
MCR P15,0,R0,C8,C5,0 ; Invalidate the entire instruction TLB
MCR P15,0,R1,C10,C4,0 ; Translate virtual address (R1) and lock into
; instruction TLB
MCR P15,0,R2,C10,C4,0 ; Translate
; virtual address (R2) and lock into instruction TLB
MCR P15,0,R3,C10,C4,0 ; Translate virtual address (R3) and lock into
; instruction TLB
CPWAIT
; The MMU is guaranteed to be updated at this point; the next instruction will
; see the locked instruction TLB entries.