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Intel
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IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 559
AHB Queue Manager (AQM)—Intel
®
IXP42X product line and IXC1100 control plane processors
21.4.1 Queue Control
The queues are implemented as circular buffers where adding an entry is performed by
a write to a queue and removing an entry is performed by a read from a queue. Entries
are read from a queue in the same order in which they were written to the queue. The
read/write pointers track the removal/addition of entries from/to a queue. The queue
control performs the autonomous access of the queues. External agents wanting to
access a queue, will perform an AHB read or write to the Queue Access Register
locations. As a result of the access to these locations, the AQM will perform the
requested access to the queue in SRAM. Support is provided for 64 queues. Upon
receiving a queue read or queue write from the AHB interface, queue control fetches
the selected queue configuration from SRAM. The queues or circular buffers will reside
in internal SRAM. Configuration for each queue will consists of:
• A Base Address – this is the address where the queue starts and is configurable for
placing the queue buffer on any 16 word boundary within the SRAM address range
of 000H to 7C0H (word address).
• A Write Pointer – this is a pointer to the next queue location to be written and is
maintained by queue control.
• A Read Pointer – this is a pointer to the next location to be read and is maintained
by queue control.
• Queue Entry Size – this indicates size of each queue entry and is configurable for 1,
2, or 4 words.
• Queue Size – this indicates the number of words allocated to the queue and is
configurable for 16, 32, 64 or 128 words.
• NE watermark – this field indicates the maximum number of occupied entries for
which a queue is considered to be nearly empty. It can be set to 0, 1, 2, 4, 8, 16,
32, or 64 entries.
• NF watermark – this field indicates the maximum number of empty entries for
which a queue is considered to be nearly full. It can be set to 0, 1, 2, 4, 8, 16, 32,
or 64 entries.
To access any given queue, after the selected queue configuration is read from SRAM,
the queue base address is summed with the read or write pointer to form the queue
address. If the queue isn’t empty, when the request is a read, or full, when the request
is a write, queue control will perform the requested queue access at the calculated
queue address. If the request is a read, the queue data read from SRAM at the
calculated queue address is passed to the AHB interface for the corresponding data
acknowledge to the AHB read request. If the request is a write, the data from the AHB
0x00417
Queue 0 to 31 Underflow/Overflow Status Register
2 x 4 Bytes
0x00410
0x0040F
Queue 0 to 31 Interrupt Status Register
4 x 4 bytes
0x00400
0x003FF
Queue 0 to 63 Read/Write Access
64 x 16 bytes
0x00000
Table 176. AHB Queue Manager Memory Map