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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 149
Intel XScale
®
Processor—Intel
®
IXP42X product line and IXC1100 control plane processors
The MIAxy instruction performs one16-bit signed multiply and accumulates these to a
single 40-bit accumulator. x refers to either the upper half or lower half of register Rm
(multiplicand) and y refers to the upper or lower half of Rs (multiplier). A value of 0x1
will select bits [31:16] of the register which is specified in the mnemonic as T (for top).
A value of 0x0 will select bits [15:0] of the register which is specified in the mnemonic
as B (for bottom).
MIAxy does not support unsigned multiplication; all values in Rs and Rm will be
interpreted as signed data values.
The instruction is only executed if the condition specified in the instruction matches the
condition code status.
3.8.3.1.2 Internal Accumulator Access Format
The Intel XScale processor defines a new instruction format for accessing internal
accumulators in CP0. Table 66, “Internal Accumulator Access Format” on page 150
shows that the op code falls into the coprocessor register transfer space.
The RdHi and RdLo fields allow up to 64 bits of data transfer between ARM registers
and an internal accumulator. The acc field specifies 1 of 8 internal accumulators to
transfer data to/from. The Intel XScale processor implements a single 40-bit
accumulator referred to as acc0; future implementations can specify multiple internal
accumulators of varying sizes, up to 64 bits.
Operation: if ConditionPassed(<cond>) then
if (bit[17] == 0)
<operand1> = Rm[15:0]
else
<operand1> = Rm[31:16]
if (bit[16] == 0)
<operand2> = Rs[15:0]
else
<operand2> = Rs[31:16]
acc0[39:0] = sign_extend(<operand1> * <operand2>) + acc0[39:0]
Exceptions: none
Qualifiers Condition Code
S bit is always cleared; no condition code flags are updated
Notes: Instruction timings can be found
in “Multiply Instruction Timings” on page 163.
Specifying R15 for register Rs or Rm has unpredictable results.
acc0 is defined to be 0b000 on Intel XScale processor.
Table 65. MIAxy{<cond>} acc0, Rm, Rs (Continued)