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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 387
General Purpose Input/Output (GPIO)—Intel
®
IXP42X product line and IXC1100 control plane
processors
The General-Purpose Data Output Register is a 16-bit register with a one-for-one
correspondence between the 16 bits of the General-Purpose Data Output Register and
the 16-bit GPIO. When logic 1 is written to a bit in the General-Purpose Data Output
Register — and the corresponding bit in the General-Purpose Enable Register is set to
logic 0 — logic 1 will be replicated to the corresponding GPIO. When logic 0 is written to
the same bit in the General-Purpose Data Output Register — and the corresponding bit
in the General-Purpose Enable Register is still set to a logic 0 — logic 0 will be
replicated to the corresponding GPIO.
For example, the General-Purpose Enable Register is set to hexadecimal 0xFFFFFAFF
and the General-Purpose Data Output Register is set to hexadecimal 0x00000401.
GPIO8 and GPIO 10 will be configured as outputs, GPIO8 will drive logic 0, and GPIO10
will drive logic 1.
Notice that bit 0 of the General-Purpose Data Output Register is set to logic 1. However,
GPIO0 is configured as an input so the logic 1 in the General-Purpose Data Output
Register is not replicated to GPIO0.
Reading of the current status of the GPIO can be obtained by reading the General-
Purpose Input Status Register. The General-Purpose Input Status Register is a 16-bit
register with a one-for-one correspondence between the 16 bits of the General-Purpose
Input Status Register and the 16-bit GPIO.
When reading the General-Purpose Input Status Register, the current logic value of the
GPIO will be reflected in the corresponding bits of the General-Purpose Input Status
Register. The values will be replicated regardless of the configuration of the GPIO as
defined by the General-Purpose Enable Register.
If a GPIO is configured as an output, the value driven to the output will be read when
reading the corresponding bits of the General-Purpose Input Status Register. For
example, the General-Purpose Enable Register is set to hexadecimal 0xFFFFFAFF and
the General-Purpose Data Output Register is set to hexadecimal 0x00000401 and the
GPIO pins have the following signals being supplied as inputs or driven as outputs,
hexadecimal 0xAE37 with GPIO[15:12] = A and GPIO[3:0] = 7. GPIO8 and GPIO10 are
configured as outputs as defined by the General-Purpose Enable Register. All other
GPIO pins are configured as inputs. When the General-Purpose Input Status Register is
read the value of hexadecimal 0x0000AE37 will be returned.
12.2 Using GPIO as Interrupt Inputs
The IXP42X product line and IXC1100 control plane processors GPIO may be
programmed to accept interrupts from external sources. Some of these sources may be
Ethernet or ADSL Physical interfaces. The type of interrupt can be one of five types:
• Active High – GPIO is high for more than five 66-MHz clock pulses
• Active Low – GPIO is low for more than five 66-MHz clock pulses
• Rising Edge – GPIO goes from an active low to an active high for more than five
66-MHz clock pulses
• Falling Edge – GPIO goes from an active high to an active low for more than five
66-MHz clock pulses
• Transitional (rising edge or falling edge) – Active high to active low or active low to
active high for more than five 66-MHz clock pulses
The GPIO interrupt can be detected by setting the two general-purpose interrupt type
registers (GPIT1R and GPIT2R). The general-purpose interrupt type registers are two
24-bit registers. These 24-bit interrupt type registers are broken up into 3-bit
registers.
Each 3-bit register represents one GPIO interrupt configuration: