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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 435
Ethernet MAC A—Intel
®
IXP42X product line and IXC1100 control plane processors
15.2.17 MDIO Command 3
15.2.18 MDIO Command 4
15.2.19 MDIO Status Registers
Four registers make up the 32-bit MDIO status:
• MDIO Status[31:24] — MDIO Status 4
• MDIO Status[23:16] — MDIO Status 3
• MDIO Status[15:8] — MDIO Status 2
• MDIO Status[7:0] — MDIO Status 1
The detailed bit descriptions follow the four registers’ bit maps.
Register Name: mdiocm3
Hex Offset Address: 0x C8009088 Reset Hex Value: 0x00000000
Register
Description:
MDIO Command Register
Access: Read/Write.
31 87 0
(Reserved) MDIO_COMMAND [23:16]
Register Name: mdiocm4
Hex Offset Address: 0x C800908C Reset Hex Value: 0x00000000
Register
Description:
MDIO Command Register
Access: Read/Write.
31 87 0
(Reserved) MDIO_COMMAND[31:24]
Register
MDIO Command
Bits Name Description
31 Go
Application logic sets this to 1 to start the MDIO access. This bit remains 1
during the access. When the access is finished, the Ethernet core resets this bit
to 0.
30:27 (Reserved)
26 MDIO Write
1 = MDIO write access
0 = MDIO read access.
25:21 PHY address Physical address of the PHY to be accessed.
20:16 PHY Register Register number of the PHY Register to be accessed.
15:0 Write data Write data on MDIO write accesses.