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Intel
®
IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB)
v1.1 Device Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
488 Order Number: 252480-006US
18.5.4.1 Receive FIFO Service (RFS)
The receive FIFO service bit is set if the receive FIFO has one complete data packet in it
and the packet has been error checked by the UDC. A complete packet may be
64 bytes, a short packet, or a zero packet. This bit is not cleared until all data has been
read from both buffers.
18.5.4.2 Receive Packet Complete (RPC)
The receive packet complete bit is set by the UDC when an OUT packet is received.
When this bit is set, the IR2 bit in the appropriate UDC status/interrupt register is set,
if receive interrupts are enabled.
This bit can be used to validate the other status/error bits in the Endpoint 2 Control/
Status Register. The UDCCS2[RPC] bit is cleared by writing a 1 to it. The UDC issues
NAK handshakes to all OUT tokens while this bit is set and both buffers have unread
data.
18.5.4.3 Bit 2 Reserved
Bit 2 is reserved for future use.
18.5.4.4 Bit 2 Reserved
Bit 3 is reserved for future use.
18.5.4.5 Sent Stall (SST)
The sent stall bit is set by the UDC in response to FST successfully forcing a user-
induced STALL on the USB bus. This bit is not set if the UDC detects a protocol violation
from the host PC when a STALL handshake is returned automatically. In either event,
the Intel XScale
®
processor does not intervene and the UDC clears the STALL status
when the host sends a CLEAR_FEATURE command.
Any valid data in the FIFO remains valid and the software must unload it. The endpoint
operation continues normally and does not send another STALL condition, even if the
UDCCS2[SST] bit is set. To allow the software to continue to send the STALL condition
on the USB bus, the UDCCS2[FST] bit must be set again.
The Intel XScale
®
processor writes a 1 to the sent stall bit to clear it.
18.5.4.6 Force Stall (FST)
The Intel XScale
®
processor can set the force stall bit to force the UDC to issue a STALL
handshake to all OUT tokens. STALL handshakes continue to be sent until the Intel
XScale
®
processor clears this bit by sending a Clear Feature command.
The UDCCS2[SST] bit is set when the STALL state is actually entered, but this may be
delayed if the UDC is active when the UDCCS2[FST] bit is set. The UDCCS2[FST] bit is
automatically cleared when the UDCCS2[SST] bit is set.
To ensure that no data is transmitted after the Clear Feature command is sent and the
host resumes IN requests, software must clear the transmit FIFO by setting the
UDCCS2[FTF] bit.
18.5.4.7 Receive FIFO Not Empty (RNE)
The receive FIFO not empty bit indicates that unread data remains in the receive FIFO.