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Intel
®
IXP42X product line and IXC1100 control plane processors—Universal Asynchronous
Receiver Transceiver (UART)
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
362 Order Number: 252480-006US
10.5.1.7 FIFO Control Register
FCR is a write-only register that is located at the same address as the IIR. (IIR is a
read-only register.) FCR enables/disables the transmitter/receiver FIFOs, clears the
transmitter/receiver FIFOs, and sets the receiver FIFO trigger level.
Table 138. UART Interrupt Identification Bit Level Definition
Interrupt ID Bits Interrupt SET/RESET Function
3210Priority Type Source Reset Control
0 0 0 1 - None No Interrupt is pending -
0110Highest
Receiver Line
Status
Overrun Error, Parity Error,
Framing Error, Break Interrupt.
Reading the Line Status Register.
0100
Second
Highest
Received Data
Available.
Non-FIFO mode: Receive Buffer is
full.
FIFO mode: Trigger level was
reached.
Non-FIFO mode: Reading the Receiver
Buffer Register.
FIFO mode: Reading bytes until
Receiver FIFO drops below trigger level
or setting RESETRF bit in FCR register.
1100
Second
Highest
Character Time-
out indication.
FIFO Mode only: At least 1
character is in receiver FIFO and
there was no activity for a time
period.
Reading the Receiver FIFO or setting
RESETRF Bit in FCR Register.
0010
Third
Highest
Transmit FIFO
Data Request
Non-FIFO mode: Transmit Holding
Register Empty
FIFO mode: Transmit FIFO has half
or less than half data.
Reading the IIR Register (if the source
of the interrupt) or writing into the
Transmit Holding Register.
Reading the IIR Register (if the source
of the interrupt) or writing to the
Transmitter FIFO.
0000
Fourth
Highest
Modem Status
Clear to Send, Data Set Ready,
Ring Indicator, Received Line
Signal Detect
Reading the Modem Status Register.
Register Name: FCR
Hex Offset Address: 0xC800 1008 Reset Hex Value: 0x00000000
Register
Description:
FIFO Control Register
Access: Write Only.
31 8765 3210
(Reserved) ITL (Rsvd)
RESETTF
RESETRF
TRFIFOE