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Intel
®
IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB)
v1.1 Device Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
520 Order Number: 252480-006US
18.5.20.7 Endpoint 6 Interrupt Request (IR6)
The interrupt request bit gets set if the IM6 bit in the UDC Interrupt Control Register is
cleared and the IN packet complete (TPC) in UDC endpoint 6 control/status register
gets set.
The IR6 bit is cleared by writing a 1 to it.
18.5.20.8 Endpoint 7 Interrupt Request (IR7)
The interrupt request bit is set if the IM7 bit in the UDC Interrupt Control Register is
cleared and the OUT packet ready bit (RPC) in the UDC Endpoint 7 Control/Status
Register is set.
The IR7 bit is cleared by writing a 1 to it.
Register Name: USIR0
Hex Offset Address: 0 x C800B058 Reset Hex Value: 0x00000000
Register
Description:
Universal Serial Bus Device Controller Interrupt Status Register 0
Access: Read/Write and Read-Only
Bits
31 876543210
(Reserved)
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0
X 00000000
Resets (Above)
Register
USIR0
Bits Name Description
31:8 Reserved for future use.
7IR7
Interrupt Request Endpoint 7 (read/write 1 to clear).
1 = Endpoint 7 needs service.
6IR6
Interrupt Request Endpoint 6 (read/write 1 to clear).
1 = Endpoint 6 needs service.
5IR5
Interrupt Request Endpoint 5 (read/write 1 to clear).
1 = Endpoint 5 needs service.
4IR4
Interrupt Request Endpoint 4 (read/write 1 to clear).
1 = Endpoint 4 needs service.
3IR3
Interrupt Request Endpoint 3 (read/write 1 to clear).
1 = Endpoint 3 needs service.
2IR2
Interrupt Request Endpoint 2 (read/write 1 to clear).
1 = Endpoint 2 needs service.
1IR1
Interrupt Request Endpoint 1 (read/write 1 to clear).
1 = Endpoint 1needs service.
0IR0
Interrupt Request Endpoint 0 (read/write 1 to clear).
1 = Endpoint 0 needs service.