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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor—
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
16 Order Number: 252480-006US
18.5.27.1 Endpoint 9 Byte Count (BC[7:0]).............................................526
18.5.28 UDC Byte Count Register 12 (UBCR12) ..................................................527
18.5.28.1 Endpoint 12 Byte Count (BC[7:0])...........................................527
18.5.29 UDC Byte Count Register 14 (UBCR14) ..................................................528
18.5.29.1 Endpoint 14 Byte Count (BC[7:0])...........................................528
18.5.30 UDC Endpoint 0 Data Register (UDDR0).................................................528
18.5.31 UDC Data Register 1 (UDDR1)..............................................................529
18.5.32 UDC Data Register 2 (UDDR2)..............................................................529
18.5.33 UDC Data Register 3 (UDDR3)..............................................................530
18.5.34 UDC Data Register 4 (UDDR4)..............................................................531
18.5.35 UDC Data Register 5 (UDDR5)..............................................................531
18.5.36 UDC Data Register 6 (UDDR6)..............................................................532
18.5.37 UDC Data Register 7 (UDDR7)..............................................................532
18.5.38 UDC Data Register 8 (UDDR8)..............................................................533
18.5.39 UDC Data Register 9 (UDDR9)..............................................................533
18.5.40 UDC Data Register 10 (UDDR10) ..........................................................534
18.5.41 UDC Data Register 11..........................................................................535
18.5.42 UDC Data Register 12 (UDDR12) ..........................................................535
18.5.43 UDC Data Register 13 (UDDR13) ..........................................................536
18.5.44 UDC Data Register 14 (UDDR14) ..........................................................536
18.5.45 UDC Data Register 15 (UDDR15) ..........................................................537
19.0 UTOPIA Level-2......................................................................................................538
19.1 UTOPIA Transmit Module ..................................................................................540
19.2 UTOPIA Receive Module....................................................................................543
19.3 UTOPIA-2 Coprocessor / NPE Coprocessor: Bus Interface ......................................545
19.4 MPHY Polling Routines ......................................................................................546
19.5 UTOPIA Level-2 Clocks .....................................................................................546
20.0 JTAG Interface.......................................................................................................548
20.1 TAP Controller .................................................................................................548
20.1.1 Test-Logic-Reset State ..........................................................................549
20.1.2 Run-Test/Idle State ..............................................................................550
20.1.3 Select-DR-Scan State............................................................................550
20.1.4 Capture-DR State .................................................................................550
20.1.5 Shift-DR State......................................................................................550
20.1.6 Exit1-DR State .....................................................................................551
20.1.7 Pause-DR State ....................................................................................551
20.1.8 Exit2-DR State .....................................................................................551
20.1.9 Update-DR State ..................................................................................551
20.1.10 Select-IR-Scan State...........................................................................552
20.1.11 Capture-IR State ................................................................................552
20.1.12 Shift-IR State.....................................................................................552
20.1.13 Exit1-IR State ....................................................................................552
20.1.14 Pause-IR State ...................................................................................552
20.1.15 Exit2-IR State ....................................................................................553
20.1.16 Update-IR State .................................................................................553
20.2 JTAG Instructions ............................................................................................553
20.3 Data Registers.................................................................................................554
20.3.1 Boundary Scan Register.........................................................................555
20.3.2 Instruction Register ..............................................................................555
20.3.3 JTAG Device ID Register ........................................................................555
21.0 AHB Queue Manager (AQM) ...................................................................................556
21.1 Overview........................................................................................................556
21.2 Feature List ....................................................................................................556