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Intel
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IXP42X product line and IXC1100 control plane processors—PCI Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
218 Order Number: 252480-006US
6.2 PCI Controller Configured as Option
The IXP42X product line and IXC1100 control plane processors can be configured as an
option function on the PCI bus. As with configuring the PCI Controller as a host
functions, the IXP42X product line and IXC1100 control plane processors, functioning
as an option does not require the Internal Arbiter function in the PCI Controller to be
enabled. Therefore, the Internal Arbiter can be enabled independently and the host/
option configuration can be selected independently. The option function is selected
similarly to the manner in which the host function is selected. (For more details, see
“PCI Controller Configured as Host” on page 213.)
If the IXP42X product line and IXC1100 control plane processors are configured as an
option, an external PCI Host will want to access the PCI Configuration Space of the
IXP42X product line and IXC1100 control plane processors. The PCI Host will complete
these accesses using PCI Configuration Cycles. However, if the IXP42X product line and
IXC1100 control plane processors receive Configuration Cycles prior to being initialized,
improper PCI bus configuration may occur.
To prevent this event from occurring, the IXP42X product line and IXC1100 control
plane processors can refuse to accept configuration cycles from an external source by
programming bit 15 of the PCI Controller Control and Status (PCI_CSR) Register. Bit 15
of the PCI Controller Control and Status (PCI_CSR) Register is the Initialization
Complete bit. When bit 15 is set to logic 0, the PCI Controller Target Interface will
issue retries to PCI Configuration cycles. When bit 15 is set to logic 1, PCI Configuration
Cycles will be accepted.
In Option mode, the PCI bus initialization and bus enumeration will be performed by an
external host processor, not the IXP42X product line and IXC1100 control plane
processors. However, the processor still has a boot sequence and there are several PCI
Configuration registers that must be "initialized" by the Intel XScale processor before
the external host starts the PCI initialization. For example, the pci_sidsvid (Subsystem
ID and Vendor ID). This register is read-only from the external host processor but is
read-write from the Intel XScale processor because its contents are application
dependent. So when the IXP42X product line and IXC1100 control plane processors
comes out of reset in HOST mode, the PCI Configuration registers are accessible from
the Intel XScale processor and inaccessible from the PCI bus. (Note: by inaccessible
from the PCI bus, that the IXP42X product line and IXC1100 control plane processors
will respond to any bus cycle with a RETRY). This is necessary because the external
host cannot be allowed to read any of the PCI Configuration registers before they have
been initialized to valid values. Once the registers (like pci_sidsvid) are initialized, S/W
writes a 1 to the IC (Init Complete) bit of pci_csr which makes the PCI Configuration
Registers accessible from PCI but inaccessible from the Intel XScale processor. So the
complete sequence is:
1. Exit reset in Option mode (pci_csr.IC = 0, PCI cycles Retried, Intel XScale processor
has access to PCI Configuration registers)
2. The Intel XScale processor initializes PCI Configuration registers as appropriate.
3. Intel XScale processor writes a 1 to pci_csr.IC (PCI cycles now accepted, PCI
Configuration registers not accessible from Intel XScale processor)
4. External host initialization of IXP42X product line and IXC1100 control plane
processors PCI Configuration Registers can proceed.
The Initialization Complete bit allows time for the IXP42X product line and IXC1100
control plane processors to configure the chip prior to accepting cycles from an external
PCI device. If initialization is not completed in the first 2
25
PCI clocks after the PCI
reset signal is de-asserted, the possibility exists for the external PCI Host to assume
that no PCI device is resident or active at this particular IDSEL.