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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 213
PCI Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
gaining access to the South AHB Master Controller’s services, then the PCI Target
interface would gain access to the South AHB Master Controller’s services again,
followed by the second DMA channel gaining access to the South AHB Master
Controller’s services, etc.
On the second level of arbitration for the South AHB Master Controller’s services, the
two DMA channels will alternate for priority access. DMA channel 0 would gain access
to the South AHB Master Controller’s services first, followed by DMA channel 1, and
then DMA channel 0, etc. This arbitration scheme balances the high-bandwidth DMA
traffic with what should be lower bandwidth PCI Target Interface traffic and is only used
in cases where contention exists. For instance, if there are only PCI Target Interface
requests being received by the South AHB Master Controller. The PCI Target would
continually get access to the South AHB Master Controller until a DMA request is
detected.
The PCI Controller also contains two configuration spaces. The PCI Controller Control
and Status Register (CSR) configuration space is used to configure the PCI Controller,
initiate single cycle PCI transactions using the non-pre-fetch registers, operate the DMA
channels, report PCI Controller status, and allow access to the PCI Controller PCI
Configuration Registers. The PCI Configuration Space is a 64-byte, PCI type-0
configuration space that supports a single function.
The PCI Configuration Space can be written or read using registers defined in the
Control and Status Registers when the IXP42X product line and IXC1100 control plane
processors are configured as a PCI Host. An external PCI Master using PCI
Configuration Cycles can write or read the PCI Configuration Space when the IXP42X
product line and IXC1100 control plane processors are configured as an Option. The
PCI Configuration Space may be accessed by the Intel XScale processor or the PCI bus
but never by both at the same time.
6.1 PCI Controller Configured as Host
The IXP42X product line and IXC1100 control plane processors can be configured as a
host function on the PCI bus. Configuring the IXP42X product line and IXC1100 control
plane processors as a host does not require the internal PCI arbiter function in the PCI
Controller to be enabled.
The first step to using the PCI interface in any mode of operation is to determine the
mode of operation and then configure the interface. The PCI bus mode of operation can
be obtained by reading bit 0 of the PCI Controller Control and Status Register
(PCI_CSR). If bit 0 of the PCI Controller Control and Status Register (PCI_CSR) is set to
logic 0, the IXP42X product line and IXC1100 control plane processors is required to
function as an Option on the PCI bus. If bit 0 of the PCI Controller Control and Status
Register (PCI_CSR) is set to logic 1, the IXP42X product line and IXC1100 control plane
processors is required to function as the Host on the PCI bus.
Bit 0 of the PCI Controller Control and Status Register (PCI_CSR) will be set by the
logic level contained on Expansion Bus Address Bus bit 1 at the de-assertion of the
reset signal supplied to the IXP42X product line and IXC1100 control plane processors.
The internal arbiter will be enabled/disabled based on the logic level contained on
Expansion Bus Address Bus bit 2 at the de-assertion of the reset signal supplied to the
IXP42X product line and IXC1100 control plane processors. The PCI Controller Control
and Status Register (PCI_CSR) bit 1 captures the logic level contained on Expansion
Bus Address Bus bit 2 at the de-assertion of reset.
If bit 1 of the PCI Controller Control and Status Register (PCI_CSR) is set to logic 1, the
IXP42X product line and IXC1100 control plane processors’s internal arbiter is enabled.
If bit 1 of the PCI Controller Control and Status Register (PCI_CSR) is set to logic 0, the
IXP42X product line and IXC1100 control plane processors’ Internal Arbiter is disabled.