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Intel
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IXP42X product line and IXC1100 control plane processors—Intel XScale
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Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
48 Order Number: 252480-006US
3.1.3 MMU Control
3.1.3.1 Invalidate (Flush) Operation
The entire instruction and data TLB can be invalidated at the same time with one
command or they can be invalidated separately. An individual entry in the data or
instruction TLB can also be invalidated. See Table 19, “TLB Functions” on page 82 for a
listing of commands supported by the Intel XScale processor.
Globally invalidating a TLB will not affect locked TLB entries. However, the invalidate-
entry operations can invalidate individual locked entries. In this case, the locked
contents remain in the TLB, but will never “hit” on an address translation. Effectively,
creating a hole is in the TLB. This situation may be rectified by unlocking the TLB.
3.1.3.2 Enabling/Disabling
The MMU is enabled by setting bit 0 in coprocessor 15, register 1 (Control Register).
When the MMU is disabled, accesses to the instruction cache default to cacheable
accesses and all accesses to data memory are made non-cacheable.
A recommended code sequence for enabling the MMU is shown in Example 1 on
page 49.
Table 6. Valid MMU and Data/Mini-Data Cache Combinations
MMU Data/mini-data Cache
Off Off
On Off
On On