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Intel
®
IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB)
v1.1 Device Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
506 Order Number: 252480-006US
18.5.13.1 Transmit FIFO Service (TFS)
The transmit FIFO service bit is active if one or fewer data packets remain in the
transmit FIFO. TFS is cleared when two complete packets of data remain in the FIFO. A
complete packet of data is signified by loading 64 bytes of data or by setting
UDCCS11[TSP].
18.5.13.2 Transmit Packet Complete (TPC)
The transmit packet complete bit is set by the UDC when an entire packet is sent to the
host. When this bit is set, the IR11 bit in the appropriate UDC status/interrupt register
is set if transmit interrupts are enabled.
This bit can be used to validate the other status/error bits in the Endpoint 11 Control/
Status Register. The UDCCS11[TPC] bit is cleared by writing a 1 to it. This clears the
interrupt source for the IR11 bit in the appropriate UDC status/interrupt register, but
the IR11 bit must also be cleared.
Setting this bit does not prevent the UDC from transmitting the next buffer. The UDC
issues NAK handshakes to all IN tokens if this bit is set and neither buffer has been
triggered by writing 64 bytes or setting UDCCS11[TSP].
18.5.13.3 Flush Tx FIFO (FTF)
The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx
FIFO bit is set when software writes a 1 to it or when the host performs a
SET_CONFIGURATION or SET_INTERFACE.
The bit’s read value is 0.
18.5.13.4 Transmit Underrun (TUR)
The transmit underrun bit is set if the transmit FIFO experiences an underrun. When
the UDC experiences an underrun, NAK handshakes are sent to the host.
UDCCS11[TUR] does not generate an interrupt and is for status only.
UDCCS11[TUR] is cleared by writing a 1 to it.
18.5.13.5 Sent STALL (SST)
The sent stall bit is set by the UDC in response to FST successfully forcing a user-
induced STALL on the USB bus. This bit is not set if the UDC detects a protocol violation
from the host PC when a STALL handshake is returned automatically. In either event,
the Intel XScale
®
processor does not intervene and the UDC clears the STALL status
when the host sends a CLEAR_FEATURE command.
The endpoint operation continues normally and does not send another STALL condition,
even if the UDCCS11[SST] bit is set. To allow the software to continue to send the
STALL condition on the USB bus, the UDCCS11[FST] bit must be set again.
The Intel XScale
®
processor writes a 1 to the sent stall bit to clear it.
18.5.13.6 Force STALL (FST)
The Intel XScale
®
processor can set the force stall bit to force the UDC to issue a STALL
handshake to all IN tokens. STALL handshakes continue to be sent until the Intel
XScale
®
processor clears this bit by sending a Clear Feature command.