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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 525
Universal Serial Bus (USB) v1.1 Device Controller—Intel
®
IXP42X product line and IXC1100
control plane processors
18.5.24.1 Endpoint 2 Byte Count (BC[7:0])
The byte count is updated after each byte is read. When software receives an interrupt
that indicates the endpoint has data, it can read the byte count register to determine
the number of bytes that remain to be read. The number of bytes that remain in the
input buffer is equal to the byte count +1.
18.5.25 UDC Byte Count Register 4 (UBCR4)
The Byte-Count Register maintains the remaining byte count in the active buffer of out
endpoint 4.
18.5.25.1 Endpoint 4 Byte Count (BC[7:0])
The byte count is updated after each byte is read. When software receives an interrupt
that indicates the endpoint has data, it can read the byte count register to determine
the number of bytes that remain to be read.
The number of bytes that remain in the input buffer is equal to the byte count +1.
Register Name: UBCR2
Hex Offset Address: 0 x C800B068 Reset Hex Value: 0x00000000
Register
Description:
Universal Serial Bus Device Endpoint 2 Byte Count
Access: Read-Only
Bits
31 87 0
(Reserved) BC[7:0]
X 00000000
Resets (Above)
Register
UBCR2
Bits Name Description
31:8 (Reserved)
7:0 BC
Byte Count (read-only).
Number of bytes in the FIFO is Byte Count plus 1 (BC+1)
Register Name: UBCR4
Hex Offset Address: 0 x C800B06C Reset Hex Value: 0x00000000
Register
Description:
Universal Serial Bus Device Endpoint 4 Byte Count
Access: Read-Only
Bits
31 87 0
(Reserved) BC[7:0]
X 00000000
Resets (Above)