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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor—
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
14 Order Number: 252480-006US
18.5.9.1 Receive FIFO Service (RFS) ......................................................498
18.5.9.2 Receive Packet Complete (RPC).................................................498
18.5.9.3 Bit 2 Reserved ........................................................................498
18.5.9.4 Bit 3 Reserved ........................................................................498
18.5.9.5 Sent Stall (SST) ......................................................................498
18.5.9.6 Force Stall (FST) .....................................................................498
18.5.9.7 Receive FIFO Not Empty (RNE)..................................................499
18.5.9.8 Receive Short Packet (RSP) ......................................................499
18.5.10 UDC Endpoint 8 Control/Status Register (UDCCS8)..................................500
18.5.10.1 Transmit FIFO Service (TFS) ...................................................500
18.5.10.2 Transmit Packet Complete (TPC) ............................................500
18.5.10.3 Flush Tx FIFO (FTF) ..............................................................500
18.5.10.4 Transmit Underrun (TUR) ......................................................500
18.5.10.5 Bit 4 Reserved .....................................................................500
18.5.10.6 Bit 5 Reserved .....................................................................501
18.5.10.7 Bit 6 Reserved .....................................................................501
18.5.10.8 Transmit Short Packet (TSP)...................................................501
18.5.11 UDC Endpoint 9 Control/Status Register (UDCCS9).................................502
18.5.11.1 Receive FIFO Service (RFS) ...................................................502
18.5.11.2 Receive Packet Complete (RPC)..............................................502
18.5.11.3 Receive Overflow (ROF) ........................................................502
18.5.11.4 Bit 3 Reserved .....................................................................502
18.5.11.5 Bit 4 Reserved .....................................................................502
18.5.11.6 Bit 5 Reserved ......................................................................502
18.5.11.7 Receive FIFO Not Empty (RNE)...............................................502
18.5.11.8 Receive Short Packet (RSP) ....................................................502
18.5.12 UDC Endpoint 10 Control/Status Register (UDCCS10) ..............................503
18.5.12.1 Transmit FIFO Service (TFS) ...................................................503
18.5.12.2 Transmit Packet Complete (TPC) .............................................503
18.5.12.3 Flush Tx FIFO (FTF) ...............................................................504
18.5.12.4 Transmit Underrun (TUR) .......................................................504
18.5.12.5 Sent STALL (SST)..................................................................504
18.5.12.6 Force STALL (FST).................................................................504
18.5.12.7 Bit 6 Reserved ......................................................................504
18.5.12.8 Transmit Short Packet (TSP)...................................................505
18.5.13 UDC End point 11 Control/Status Register (UDCCS11) .............................505
18.5.13.1 Transmit FIFO Service (TFS) ...................................................506
18.5.13.2 Transmit Packet Complete (TPC) .............................................506
18.5.13.3 Flush Tx FIFO (FTF) ...............................................................506
18.5.13.4 Transmit Underrun (TUR) .......................................................506
18.5.13.5 Sent STALL (SST)..................................................................506
18.5.13.6 Force STALL (FST).................................................................506
18.5.13.7 Bit 6 Reserved ......................................................................507
18.5.13.8 Transmit Short Packet (TSP)...................................................507
18.5.14 UDC Endpoint 12 Control/Status Register (UDCCS12) ..............................508
18.5.14.1 Receive FIFO Service (RFS) ....................................................508
18.5.14.2 Receive Packet Complete (RPC)...............................................508
18.5.14.3 Bit 2 Reserved ......................................................................508
18.5.14.4 Bit 3 Reserved ......................................................................508
18.5.14.5 Sent Stall (SST) ....................................................................508
18.5.14.6 Force Stall (FST) ...................................................................509
18.5.14.7 Receive FIFO Not Empty (RNE)................................................509
18.5.14.8 Receive Short Packet (RSP) ....................................................509
18.5.15 UDC Endpoint 13 Control/Status Register (UDCCS13) ..............................510
18.5.15.1 Transmit FIFO Service (TFS) ...................................................510
18.5.15.2 Transmit Packet Complete (TPC) .............................................510
18.5.15.3 Flush Tx FIFO (FTF) ...............................................................510
18.5.15.4 Transmit Underrun (TUR) .......................................................511
18.5.15.5 Bit 4 Reserved ......................................................................511