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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 285
SDRAM Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
7.3 SDRAM Memory Accesses
7.3.1 Read Transfer
When the AHBs generate a read transaction with an address located in the SDRAM
space, a read from SDRAM is initiated. The SDRAM detects the read initiation request
from the AHB. The SDRAM Interface control signals perform an SDRAM active cycle
with the appropriate row address followed by a RAS-to-CAS delay. After a RAS-to-CAS
delay of a three clocks, the SDRAM Interface control signal generates a read command
and presents the column address. The control signal then waits for a number of clocks
(CAS-to-data delay) before registering the data that is returned from the SDRAM. The
SDRAM controller performs these reads until either the end of the transfer on the AHB
or until the column address increments to hit a page-crossover condition. Upon such a
crossover condition, the SDRAM Controller terminates the transaction by performing a
Burst Terminate followed by pre-charge cycle and resumes the read transfer from the
incremented address.
7.3.1.1 Read Cycle Timing (CAS Latency of Two Cycles)
Figure 55 shows the timing cycles on the SDRAM for a read cycle with a CAS Latency of
2 Cycles.
Table 112. Data Transfer Sizes of AHB
Size Description
8 bits Byte
16 bits Half word
32 bits Word
Figure 55. SDRAM Read Example (CAS Latency of 2 Cycles)
ACTIVE
NOP
NOP
READ
NOP
NOP NOP NOP
NOP
RAS
XX
XX
CAS
XX
XX XX XX
XX
XX
XX
XX
XX XX
D0 D1 D2
D3
HI
HI
HI
HI HI
LOW LOW LOW
LOW
HI
HI
HI
HI HI
HI HI HI
HI
SDM_CLK
COMMAND
SDM_ADDR
SDM_DATA
SDM_DQM
SDM_CKE