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©2008 Advanced Micro Devices, Inc.
SMBus Module and ACPI Block (Device 20, Function 0)
AMD SB600 Register Reference Manual Proprietary Page 151
GPMConfig0 – RW – 8 bits - [PM_Reg: 32h]
Field Name Bits Default Description
ExtEvent0Config 1:0 00b These two bits configure ExtEvent0
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 ExtEvent0 to generate SMI#
10 ExtEvent0 to generate SMI# followed by SCI
11 ExtEvent0 to generate IRQ13
ExtEvent1Config 3:2 00b These two bits configure ExtEvent1
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 ExtEvent1 to generate SMI#
10 ExtEvent1 to generate SMI# followed by SCI
11 ExtEvent1 to generate IRQ13
PCIePmeConfig 5:4 00b These two bits configure PCIePme
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 PCIePme to generate SMI#
10 PCIePme to generate SMI# followed by SCI
11 PCIePme to generate IRQ13
Gpm0Config 7:6 00b These two bits configure GPM0
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 GPM0 to generate SMI#
10 GPM0 to generate SMI# followed by SCI
11 GPM0 to generate IRQ13
GPMConfig1- RW – 8 bits - [PM_Reg: 33h]
Field Name Bits Default Description
Gpm1Config 1:0 00b These two bits configure GPM1
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 GPm1 to generate SMI#
10 Gpm1 to generate SMI# followed by SCI
11 GPm1 to generate IRQ13
Gpm2Config 3:2 00b These two bits configure GPM2
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 Gpm2 to generate SMI#
10 Gpm2 to generate SMI# followed by SCI
11 GPm2 to generate IRQ13
Gpm3Config 5:4 00b These two bits configure GPM3
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 GPM3 to generate SMI#
10 GPM3 to generate SMI# followed by SCI
11 GPM3 to generate IRQ13
Gpm8Config 7:6 00b These two bits configure GPM8
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 GPM8 to generate SMI#
10 GPM8 to generate SMI# followed by SCI
11 GPM8 to generate IRQ13