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©2008 Advanced Micro Devices, Inc.
AC ’97 Controller Functional Descriptions
AMD SB600 Register Reference Manual Proprietary Page 222
Counter - R - 32 bits - [MEM_Reg: 18h]
Field Name Bits Default Description
Slot Counter 3:0 0h The current slot number (0-12) which the AC97
controller handling.
Reserved 7:4 0h
Bit Clock Counter 12:8 00h For the tag slot, the value changes from 0 to F. For
other slots the value changes from 0 to 20.
Reserved 31:13 00000h
Counter Register:
Input FIFO Threshold - RW - 32 bits - [MEM_Reg: 1Ch]
Field Name Bits Default Description
Input Threshold 4:0 00h Threshold value for the Input Channel's FIFOs. (FIFO
size 16x20)
Reserved 31:5 0000000h
Input FIFO Threshold Register: Input DMA's FIFOs threshold value.
Input DMA Link List Pointer - RW - 32 bits - [MEM_Reg: 20h]
Field Name Bits Default Description
in DMA LL ptr en 0 0b Input DMA Link List Pointer enable
in DMA LL Pointer 31:1 0000_0000h Pointer to the start of the Link List - to the first DT.
Input DMA Link List Pointer Register:
Input DMA DT Start - R - 32 bits - [MEM_Reg: 24h]
Field Name Bits Default Description
in DMA DT start 31:0 0000_0000h Pointer to the start of data associated with current DT
for the input DMA
Input DMA Discrete Table (DT) Start Pointer Register.
Input DMA DT Next - R - 32 bits - [MEM_Reg: 28h]
Field Name Bits Default Description
in DMA DT next 31:0 0000_0000h Pointer to the next DT for the input DMA
Input DMA DT Next Pointer Register.
Input DMA DT Current - R - 32 bits - [MEM_Reg: 2Ch]
Field Name Bits Default Description
in DMA DT current 31:0 0000_0000h Pointer to the currently accessing memory address for
the input DMA
Input DMA DT Current Pointer Register.
Input DMA DT Size & FIFO Info - R - 32 bits - [MEM_Reg: 30h]
Field Name Bits Default Description
in DMA DT size 15:0 0000h Data size of DT for input DMA.
in FIFO Used 20:16 00h Number of filled FIFO entries of input DMA.
in FIFO Free 25:21 06h Number of free FIFO entries of input DMA.
in DMA State 28:26 0h Current state of the in DMA
Reserved 31:20 000h
Input DMA DT Size & FIFO info Register: Size of data associated with DT for input channels and number of FIFO
entries free and used for the input channels.