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©2008 Advanced Micro Devices, Inc.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual Proprietary Page 56
HcInterruptStatus – RW - 32 bits - [MEM_Reg : 0Ch]
Field Name Bits Default HCD HC Description
SO 0 0b RW RW
SchedulingOverrun
This bit is set when the USB schedule for the current
Frame overruns and after the update of
HccaFrameNumber. A scheduling overrun will also
cause the SchedulingOverrunCount of
HcCommandStatus to be incremented.
WDH 1 0b RW RW
WritebackDoneHead
This bit is set immediately after HC has written
HcDoneHead to HccaDoneHead. Further updates of
the HccaDoneHead will not occur until this bit has
been cleared. HCD should only clear this bit after it
has saved the content of HccaDoneHead.
SF 2 0b RW RW
StartofFrame
This bit is set by HC at each start of a frame and after
the update of HccaFrameNumber. HC also generates
a SOF token at the same time.
RD 3 0b RW RW
ResumeDetected
This bit is set when HC detects that a device on the
USB is asserting resume signaling. It is the transition
from no resume signaling to resume signaling
causing this bit to be set. This bit is not set when
HCD sets the
USBRESUME state.
UE 4 0b RW RW
UnrecoverableError
This bit is set when HC detects a system error not
related to USB. HC should not proceed with any
processing nor signaling before the system error has
been corrected. HCD clears this bit after HC has
been reset.
FNO 5 0b RW RW
FrameNumberOverflow
This bit is set when the MSb of HcFmNumber (bit 15)
changes value, from 0 to 1 or from 1 to 0, and after
HccaFrameNumber has been updated.
RHSC 6 0b RW RW
RootHubStatusChange
This bit is set when the content of HcRhStatus or the
content of any of HcRhPortStatus
[NumberofDownstreamPort] has changed.
Reserved 29:7 Reserved
OC 30 0b RW RW
OwnershipChange
This bit is set by HC when HCD sets the
OwnershipChangeRequest field in
HcCommandStatus. This event, when unmasked, will
always generate an System Management Interrupt
(SMI) immediately.
This bit is tied to 0b when the SMI pin is not
implemented.
Reserved 31 Reserved
HcInterruptEnable - 32 bits - [MEM_Reg : 10h]
Field Name Bits Default HCD HC Description
SO 0 0b RW RW 0 - Ignore
1 - Enable interrupt generation due to Scheduling
Overrun.
WDH 1 0b RW RW 0 - Ignore
1 - Enable interrupt generation due to HcDoneHead
Writeback.
SF 2 0b RW RW 0 - Ignore
1 - Enable interrupt generation due to Start of Frame.