AMD SB600 Cash Register User Manual


 
©2008 Advanced Micro Devices, Inc.
Real Time Clock (RTC)
AMD SB600 Register Reference Manual Proprietary Page 291
Register Name Offset Address
Register A 0Ah
Register B 0Bh
Register C 0Ch
Register D 0Dh
AltCentury (when DV0=0) 32h
Century (when DV0=1) 48h
Extended RAM Address Port 50h
Extended RAM Data Port 53h
RTC Time Clear 7Eh
RTC RAM Enable 7Fh
Registers that are implemented in the internal RTC are described below.
Seconds - RW – 8 bits - [RTC_Reg: 00h]
Field Name Bits Default Description
Seconds 7:0 00h Binary-Code-Decimal format. Range:00 – 59
This register can be set by software (SET bit of Register B = 1)
or can be automatically updated by hardware every second.
When set by software, hardware updating is disabled.
Seconds register
Seconds Alarm - RW – 8 bits - [RTC_Reg: 01h]
Field Name Bits Default Description
Seconds Alarm 7:0 00h Binary-Code-Decimal format.
If SET bit = 1, Seconds Alarm Register will never match with
Seconds Register, else
If bits [7:6] = [11], Seconds Alarm Register always matches
with Seconds Register.
Seconds Alarm register
Minutes - RW – 8 bits - [RTC_Reg: 02h]
Field Name Bits Default Description
Minutes 7:0 00h Binary-Code-Decimal format. Range:00 – 59
This register can be set by software (SET bit of Register B = 1)
or can be automatically updated by hardware every minute.
When set by software, hardware updating is disabled.
Minutes register
Minutes Alarm - RW – 8 bits - [RTC_Reg: 03h]
Field Name Bits Default Description
Minutes Alarm 7:0 00h Binary-Code-Decimal format.
If SET bit = 1, Minutes Alarm Register will never match with
Minutes Register, else
If bits [7:6] = [11], Minutes Alarm Register always matches
with Minutes Register.
Minutes Alarm register
Hours - RW – 8 bits - [RTC_Reg: 04h]
Field Name Bits Default Description
Hours 7:0 00h Binary-Code-Decimal format. Range:00 – 23
This register can be set by software (SET bit of Register B = 1)
or can be automatically updated by hardware every hour.
When set by software, hardware updating is disabled.