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©2008 Advanced Micro Devices, Inc.
Appendix A: AC97 Audio FAQs
AMD SB600 Register Reference Manual Proprietary Page 299
Appendix A: AC97 Audio FAQs
Q: What is the descriptor table (DT) data structure in memory?
A: Data Pointer (first dword); Size, Status (2nd dword); Next descriptor pointer (3rd dword). The Data pointer
points to the beginning of a data block. In the 2nd dword, Size uses [31:16], and Status uses bit[0]. The other
bits are 0. Size tells the data block size pointed by the Data Pointer. The Status bit can be set to 1 by
hardware when the current data block is completed. Software can check this bit to know the progress of the
hardware and plan ahead. Another way to accomplish this is to set the status bit in the register so the
software will check that register. The Next descriptor pointer points to the next descriptor table.
Q: Where is the status bit updated each time a data block is completed?
A: For audio input:
When reg0x04[1]=1 and reg0x08[3]=0: the status bit is updated in reg0x00[1]. When reg0x04[1]=1 and
reg0x08[3]=1: the status bit is updated in memory.
For audio output:
When reg0x04[1]=1 and reg0x08[3]=0: the status bit is updated in reg0x00[3]. When reg0x04[1]=1 and
reg0x08[3]=1: the status bit is updated in memory.
Q: I set the appropriate bits so that the interrupt register (0x00) has the “out DMA status” bit set at the end of
a data block and an interrupt happens. Is this necessary in order to cause an interrupt to happen?
A: Yes.
Q: Is it possible to have both an interrupt occur and the status bit in memory set at the same time?
A: No. The Status bit can be set either in memory or in register, but not both.
Q: What is a Linked List?
A: When a series of DTs are linked, it becomes a Linked List whose last DT has an invalid value of 0 as its
Next Descriptor to signal the end of the chain.
Q: How can I determine whether a Linked List is complete?
A: This is determined by examining bit 0 of the current DT control block status word in memory to see if the
DMA controller is finished with it, and then you examine the “Output DMA DT Next” register (0x40) to see if
this was the last one in the chain or not. When both conditions are satisfied, you can tell the Linked List is
complete.
Q: I am trying to determine if the DMA controller is idle or not. It seems that the “Output DMA DT Size and
State” register (0x48) has 3 bits in it called “out DMA state”. Can I look at it alone to determine whether the
current chain is complete?
A: No. There is no way to look at the DMA state alone to determine whether the current chain is completed.
The state machine returns 0 every time a data block is complete and checks whether the next DT or next
Linked List is valid. If invalid, the state machine stops there; else it starts to consume the next DT block. To
determine whether the chain is complete you need to make sure of the following: (a) the current Data block is
complete by checking status bit or DMA state=0, and (b) next DT is invalid. Unfortunately there is no quicker
way. The state machine runs as follows: 0 (idle) -> 1 (descriptor table load) -> 2 (Data request) -> 3 (data
load) -> 4 (status bit update) -> 0 (idle).
Q: What’s the relation between Register (0x48) “Output DMA DT Size and State” and register (0x8C) “Output
DMA Fifo Info”?
A: Originally there was only reg0x48, no reg0x8C. Later the decision was made to increase the size of FIFO
to 90 deep. As a result, reg0x48 became insufficient. Its fields “out FIFO Used” and “out FIFO Free” were not
wide enough to express the number 90. So the decision was made to move the two fields to the new register
0x8C.