Filter
Top Products
©2008 Advanced Micro Devices, Inc.
AC ’97 Controller Functional Descriptions
AMD SB600 Register Reference Manual Proprietary Page 221
Modem Command - RW - 32 bits - [MEM_Reg: 08h]
Field Name Bits Default Description
Modem Command Register: Controls the operation of Audio Controller. Value of "1" in bit position enables
corresponding function. Value of "0" disables it.
Phy Status and Address - RW - 32 bits - [MEM_Reg: 0Ch]
Field Name Bits Default Description
Codec ID 1:0 00b 0 – Master AC97
1 – 1
st
slave AC97
2 – 2
nd
slave AC97
3 – Reserved
Read/Write request 2 0b 1 – Read request.
0 – Write request
Reserved 7:3 0b
Phy out address enable 8 0b 1 - Enable sending out of Physical address in next
frame
0 - Physical out address have been sent out; open to
get new value.
When the bit is 0, writing 1 to it makes it 1. Once it is 1,
writing to it is ignored. It will automatically return to 0
when physical address is sent out.
Phy out address 15:9 0b Physical out address (wont be able to write new
address until old one is send out - until Physical out
address enable is '1') (for address write bit [8] is
asserted until data send out)
Phy out Data 31:16 0000h Physical register out data (for write). When Physical
out address enabled and Write request is set (Physical
status [2]=0) then the value in this register will be send
out in slot 2
Phy Status/ Phy out address and data Register: Controls the Physical status of the AC'97 Controller and also has
the Physical out address and data to be sent with the next frame.
Input Phy Address and Data - R - 32 bits - [MEM_Reg: 10h]
Field Name Bits Default Description
Reserved 7:0 00h
Phy_in_read_flag 8 0b It is cleared whenever reg0x0Ch[8]=1 and
reg0x0C[2]=1.
It is set when input physical data (due to a physical
read) arrives.
in_Phy_addr 15:9 00h Physical address from AC'97 Codec
Input Phy data 31:16 0000h Input Physical data from AC'97 Codec.
Input Phy address and data Register:
Input Ch2 GPIO Data - R - 32 bits - [MEM_Reg: 14h]
Field Name Bits Default Description
SLOTREQ 9:0 000h The read only bits [0:9] of this field respectively come
from slot1[11:2] of AC link’s SDATA_IN0/1/2 OR’ed
together (even if slot 1 may not be valid as indicated
by slot 0[14]). These bits [0:9] respectively decide
whether slot 3~12 of SDATA_OUT is allowed or not.
0 – Slot is allowed
1 – Slot is allowed
Even if a bit in this field being 0 indicates a slot is
allowed, the controller further looks at reg0x34[9:0] to
finally decide whether the slot is enabled.
Reserved 31:10 000000h
SLOTREQ Register: