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©2008 Advanced Micro Devices, Inc.
SMBus Module and ACPI Block (Device 20, Function 0)
AMD SB600 Register Reference Manual Proprietary Page 171
K8C1ePort - RW - 16 bits - [PM_Reg: 99:98h]
Field Name Bits Default Description
K8C1ePort 15:0 0000h This register defines the 16 bit IO address for the K8 C1e
support. In AMD K8 dual core system, when both CPUs have
entered the C1e state, it will broadcast an IO cycle. BIOS can
program CPU with this address for such function. When SB
receives this IO cycle, it can automatically sequence to C2 or
C3 depending on PMIO9Ah, bits [1:0].
K8C1ePort register
EnhanceControl - RW - 8 bits - [PM_Reg: 9Ah]
Field Name Bits Default Description
K8C1eToC2En 0 0b If this bit is set, a write to the IO address defined by
K8C1ePort will cause SB to automatically sequence to C2
K8C1eToC3En 1 1b If this bit is set, a write to the IO address defined by
K8C1ePort will cause SB to automatically sequence to C3. It
is BIOS’s responsibility not to set both bits 0 and 1 to 1; only
one bit can be set to 1.
K8C3PopUpEn 2 0b If this bit is set, SB can pop up from C3 to C2 in the case of
bus mastering (DMA) instead of transitioning to C0. After
DMA, it goes back to C3 with minimum delay of LdtStartTime.
AutoArbDisEn 3 0b K8 system –
If this bit is set and K8C1eToC3En is also set, a write to the IO
address defined by K8C1ePort will cause SB automatically set
the ARB_DIS bit.
P4 system –
If this bit is set, LVL3 read will cause SB automatically set the
ARB_DIS bit.
auto_bm_rld 4 0b If this bit is set, BM_STS will cause SB to wakeup from C3/4
even if BM_RLD is not set.
auto_clr_bm_sts 5 0b If this bit is set, BM_STS will be cleared when system enters
C3/4.
FastReadEnable 6 0b This bit is to make the read from ADC as fast as possible.
HPET_Periodic 7 0b Set to 1 to enable HPET periodic mode hw support.
EnhanceControl register
K8C1eReadPort - R - 8 bits - [PM_Reg: 9Bh]
Field Name Bits Default Description
K8C1eReadPort 7:0 00h The C1e Write by CPU is stored in this register. The value
written by the C1e write can also be read from the defined IO
address
K8C1eReadPort register
MsiSignature - R - 24 bits - [PM_Reg: 9E:9Ch]
Field Name Bits Default Description
MsiSignature 19:0 00000h This defines the MSI signature SB will monitor. This
corresponds to address [39:20]. When SB sees transaction
with this address, it will issue a break event to the C state
machine if the CPU is in C2/3/4 state
Spare 21:20 00b
HPET_Version 23:22 00b Set to 11b to make HPET revision id to be 01.
MsiSignature register