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©2008 Advanced Micro Devices, Inc.
LPC ISA Bridge (Device 20, Function 3)
AMD SB600 Register Reference Manual Proprietary Page 253
IO Port Decode Enable Register 1- RW - 8 bits - [PCI_Reg: 44h]
Field Name Bits Default Description
Parallel Port Enable 5 5 0b Port enable for parallel port, 7bc-7bfh
Serial Port Enable 0 6 0b Port enable for serial port, 3f8-3ffh
Serial Port Enable 1 7 0b Port enable for serial port, 2f8-2ffh
This register controls the decoding of parallel & serial ports. Writing ‘1’ to a bit enables the corresponding IO range.
IO Port Decode Enable Register 2- RW - 8 bits - [PCI_Reg: 45h]
Field Name Bits Default Description
Serial Port Enable 2 0 0b Port enable for serial port, 220-227h
Serial Port Enable 3 1 0b Port enable for serial port, 228-22fh
Serial Port Enable 4 2 0b Port enable for serial port, 238-23fh
Serial Port Enable 5 3 0b Port enable for serial port, 2e8-2efh
Serial Port Enable 6 4 0b Port enable for serial port, 338-33fh
Serial Port Enable 7 5 0b Port enable for serial port, 3e8-3efh
Audio Port Enable 0 6 0b Port enable for audio port, 230-233h (Range 220-22fh needs to
be enabled using bits 0 and 1)
Audio Port Enable 1 7 0b Port enable for audio port, 240-253h
This register controls the decoding of serial & audio ports. Writing ‘1’ to a bit enables the corresponding IO range.
IO Port Decode Enable Register 3- RW - 8 bits - [PCI_Reg: 46h]
Field Name Bits Default Description
Audio Port Enable 2 0 0b Port enable for audio port, 260-273h
Audio Port Enable 3 1 0b Port enable for audio port, 280-293h
MIDI Port Enable 0 2 0b Port enable for MIDI port, 300-301h
MIDI Port Enable 1 3 0b Port enable for MIDI port, 310-311h
MIDI Port Enable 2 4 0b Port enable for MIDI port, 320-321h
MIDI Port Enable 3 5 0b Port enable for MIDI port, 330-331h
MSS Port Enable 0 6 0b Port enable for MSS port, 530-537h
MSS Port Enable 1 7 0b Port enable for MSS port, 604-60bh
This register controls the decoding of audio, MIDI, & MSS ports. Writing ‘1’ to a bit enables the corresponding IO
range.
IO Port Decode Enable Register 4- RW - 8 bits - [PCI_Reg: 47h]
Field Name Bits Default Description
MSS Port Enable 2 0 0b Port enable for MSS port, e80-e87h
MSS Port Enable 3 1 0b Port enable for MSS port, f40-f47h
FDC Port Enable 0 2 0b Port enable for FDC port, 3f0-3f7h
FDC Port Enable 1 3 0b Port enable for FDC port, 370-377h
Game Port Enable 4 0b Port enable for Game port, 200-20fh
KBC Port Enable 5 0b Port enable for KBC port, 60 & 64h
ACPI Micro-Controller
Port Enable
6 0b Port enable for ACPI Micro-Controller port, 62 & 66h
Ad-Lib Port Enable 7 0b Port enable for Ad-Lib port, 388-389h
This register controls the decoding of MSS, FDC, game, KBC, ACPI micro-controller, & Ad-lib ports. Writing ‘1’ to a
bit enables the corresponding IO range.
IO/Mem Port Decode Enable Register 5- RW - 8 bits - [PCI_Reg: 48h]
Field Name Bits Default Description
Super IO Configuration
Port Enable
0 0b Port enable for Super IO config port, 2e-2fh
Alternate Super IO
Configuration Port
Enable
1 0b Port enable for Alternate super IO config port, 4e-4fh
Wide Generic IO Port
Enable
2 0b Port enable for wide generic port, see register 64-65h