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©2008 Advanced Micro Devices, Inc.
Table of Contents
AMD SB600 Register Reference Manual Proprietary Page 3
Table of Contents
1 Introduction .............................................................................................................7
1.1 About this Manual........................................................................................................................... 7
1.2 Nomenclature and Conventions..................................................................................................... 7
1.2.1 Recent Updates .....................................................................................................................................7
1.2.2 Numeric Representations.......................................................................................................................7
1.2.3 Register Description...............................................................................................................................7
1.3 Features of the SB600 ................................................................................................................... 9
1.4 Block Diagrams ............................................................................................................................ 11
2 Register Descriptions: PCI Devices.....................................................................13
2.1 SATA Registers (Device 18, Function 0) ..................................................................................... 13
2.1.1 PCI Configuration Space......................................................................................................................13
2.1.2 BAR0/BAR2/BAR1/BAR3 Registers (SATA I/O Register for IDE mode)..............................................24
2.1.3 BAR4 Registers (SATA I/O Register for IDE mode).............................................................................24
2.1.4 BAR5 Registers....................................................................................................................................25
2.1.4.1 Generic Host Control ............................................................................................................................................ 25
2.1.4.2 Port Registers (One Set Per Port) ........................................................................................................................ 31
2.2 OCHI USB 1.1 and EHCI USB 2.0 Controllers ............................................................................ 44
2.2.1 OHCI Registers (Device 19, Function 0, 1, 2, 3, 4) ..............................................................................44
2.2.1.1 PCI Configuration Registers (PCI_Reg) ............................................................................................................... 44
2.2.1.2 OHCI Operational Registers (MEM_Reg)............................................................................................................. 51
2.2.2 USB Legacy Keyboard Operation ........................................................................................................66
2.2.2.1 Overview............................................................................................................................................................... 66
2.2.2.2 System Requirements .......................................................................................................................................... 67
2.2.2.3 Programming Interface ......................................................................................................................................... 68
2.2.3 EHCI Registers (Device 19, Function 5) ..............................................................................................70
2.2.3.1 PCI Configuration Registers ................................................................................................................................. 70
2.2.3.2 Host Controller Capability Registers (MEM_Reg) ................................................................................................ 79
2.2.3.3 Host Controller Operational Registers (EOR_Reg) .............................................................................................. 82
2.2.3.4 USB2.0 Debug Port Registers.............................................................................................................................. 92
2.3 SMBus Module and ACPI Block (Device 20, Function 0) ............................................................ 96
2.3.1 PCI Configuration Registers and Extended Registers..........................................................................97
2.3.1.1 PCIE Configuration Registers............................................................................................................................... 97
2.3.1.2 Extended Registers ............................................................................................................................................ 120
2.3.2 SMBus Registers ...............................................................................................................................123
2.3.3 Legacy ISA and ACPI Controller........................................................................................................126
2.3.3.1 Legacy Block Registers ...................................................................................................................................... 126
2.3.3.1.1 IO-Mapped Control Registers.....................................................................................................................126
2.3.3.1.2 Client Management Registers (Accessed through C50h and C51h) .........................................................137
2.3.3.1.3 System Reset Register (IO CF9)................................................................................................................139
2.3.3.2 Power Management (PM) Registers................................................................................................................... 139
2.3.3.3 ACPI Registers ................................................................................................................................................... 176
2.3.4 WatchDogTimer Registers .................................................................................................................181
2.3.5 ASF SM bus Host Interface Registers................................................................................................182
2.4 IDE Controller (Device 20, Function 1) ...................................................................................... 186
2.4.1 PCI Configuration Registers...............................................................................................................186
2.4.2 IDE I/O Registers ...............................................................................................................................195