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©2008 Advanced Micro Devices, Inc.
GEVENT/GPE/GPM/ExtEvent
AMD SB600 Register Reference Manual Proprietary Page 284
Pin Name
(*Note 1)
Multi-Function
Selection
Configure Bit
00 – SCI or SMI#
01 – SMI#
10 – SMI#
followed by SCI
11 - IRQ13
Trigger Configure
0–Falling edge
1–Rising edge
Enable
ACPI Event
Status
(Write 1 to ACPI
GPE00h Bit to
Clear)
Power
Domain
GEVENT2/
THRMTRIP#
/SMBALERT
#
PM IO
Reg68h[Bit 3]
0: GEVENT2
1: THRMTRIP#
PM IO
Reg30h[Bit5:4]
PM IO
Reg36h[Bit 2]
ACPI
GPE04h[Bit 2]
PM IO
Reg39h[Bit 2]
or ACPI
GPE00h[Bit 2]
S5
GEVENT3/
LPC_PME#
*Note 5 PM IO
Reg30h[Bit7:6]
PM IO
Reg36h[Bit3]
ACPI
GPE04h[Bit3]
PM IO
Reg39h[Bit3]
or ACPI
GPE00h[Bit3]
S5
GEVENT4/
PCI_PME#
*Note 5 PM IO
Reg31h[Bit1:0]
PM IO
Reg36h[Bit4]
ACPI
GPE04h[Bit4]
PM IO
Reg39h[Bit4]
or ACPI
GPE00h[Bit4]
S5
GEVENT5/
S3_STATE
SMBus
Reg64h[Bit 8]
=1 to enable
GPE
*Note 4
PM IO
Reg31h[Bit3:2]
PM IO
Reg36h[Bit 5]
ACPI
GPE04h[Bit 5]
PM IO
Reg39h[Bit 5]
or ACPI
GPE00h[Bit 5]
S5
GEVENT6/
USB_OC6#
*Note 5 PM IO
Reg31h[Bit5:4]
PM IO
Reg36h[Bit 6]
ACPI
GPE04h[Bit 6]
PM IO
Reg39h[Bit 6]
or ACPI
GPE00h[Bit 6]
S5
GEVENT7/
USB_OC7#
*Note 5 PM IO
Reg31h[Bit7:6]
PM IO
Reg36h[Bit 7]
ACPI
GPE04h[Bit 7]
PM IO
Reg39h[Bit 7]
or ACPI
GPE00h[Bit 7]
S5
GEVENT8/
WAKE#
PM IO
Reg84h[Bit 0]
0: GEVENT8
1: WAKE#
PM IO
Reg84h[Bit 1]=1
and SMBus Reg
64h[Bit 19]=1 to
enable GPE
PM IO
Reg34h[Bit1:0]
PM IO
Reg38h[Bit 0]
ACPI
GPE04h[Bit24]
PM IO
Reg3Bh[Bit 0]
or ACPI
GPE00h[Bit24]
S5
GPM0/
USB_OC0#
SMBus
Reg64h[Bit 23]
=1 to enable
GPE
PM IO
Reg32h[Bit7:6]
PM IO
Reg37h[Bit 3]
ACPI
GPE04h[Bit19]
PM IO
Reg3Ah[Bit 3]
or ACPI
GPE00h[Bit19]
S5
GPM1/
USB_OC1#
SMBus
Reg64h[Bit 23]
=1 to enable
GPE
PM IO
Reg33h[Bit1:0]
PM IO
Reg37h[Bit 4]
ACPI
GPE04h[Bit20]
PM IO
Reg3Ah[Bit 4]
or ACPI
GPE00h[Bit20]
S5
GPM2/
USB_OC2#
SMBus
Reg64h[Bit 23]
=1 to enable
GPE
PM IO
Reg33h[Bit3:2]
PM IO
Reg37h[Bit 5]
ACPI
GPE04h[Bit21]
PM IO
Reg3Ah[Bit 5]
or ACPI
GPE00h[Bit21]
S5