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Intel
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IXP42X product line and IXC1100 control plane processors—Intel XScale
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Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
104 Order Number: 252480-006US
3.6.11.2.1 DBG.HLD_RST
The debugger uses DBG.HLD_RST when loading code into the instruction cache during
a processor reset. Details about loading code into the instruction cache are in
“Downloading Code in ICache” on page 116.
The debugger must set DBG.HLD_RST before or during assertion of the reset pin. Once
DBG.HLD_RST is set, the reset pin can be de-asserted, and the processor will internally
remain in reset. The debugger can then load debug handler code into the instruction
cache before the processor begins executing any code.
Once the code download is complete, the debugger must clear DBG.HLD_RST. This
takes the processor out of reset, and execution begins at the reset vector.
A debugger sets DBG.HLD_RST in one of two ways:
• Either by taking the JTAG state machine into the Capture_DR state, which
automatically loads DBG_SR[1] with ‘1’, then the Exit2 state, followed by the
Update_Dr state. This will set the DBG.HLD_RST, clear DBG.BRK, and leave the
DCSR unchanged (the DCSR bits captured in DBG_SR[34:3] are written back to the
DCSR on the Update_DR).
• Alternatively, a ‘1’ can be scanned into DBG_SR[1], with the appropriate value
scanned in for the DCSR and DBG.BRK.
DBG.HLD_RST can only be cleared by scanning in a ‘0’ to DBG_SR[1] and scanning in
the appropriate values for the DCSR and DBG.BRK.
3.6.11.2.2 DBG.BRK
DBG.BRK allows the debugger to generate an external debug break and
asynchronously re-direct execution to a debug handling routine.
Figure 16. SELDCSR Data Register
12
3334
TDO
TDI
DBG_SR
Capture_DR
Update_DR
DBG_REG
1
2334
35
TCK
0
0
DCSR
DBG.HLD_RST
DBG.DCSR
0
0
1
DBG.BRK
0
ignored