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Intel
®
IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB)
v1.1 Device Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
534 Order Number: 252480-006US
Because it is double-buffered, up to two packets of data may be ready. The data can be
removed from the UDC via a direct read from the Intel XScale
®
processor. If one
packet is being removed and the packet behind it has already been received, the UDC
issues a NAK to the host the next time it sends an OUT packet to Endpoint 9.
This NAK condition remains in place until a full packet space is available in the UDC at
Endpoint 9.
18.5.40 UDC Data Register 10 (UDDR10)
Endpoint 10 is an interrupt IN endpoint that is 8 bytes deep. Data must be loaded via
direct Intel XScale
®
processor writes.
Because the USB system is a host-initiator model, the host must poll Endpoint 10 to
determine interrupt conditions. The UDC can not initiate the transaction.
Register Name: UDDR9
Hex Offset Address: 0 x C800B900 Reset Hex Value: 0x00000000
Register
Description:
Universal Serial Bus Device Endpoint 9 Data Register
Access: Read
Bits
31 87 0
(Reserved) (8-Bit Data)
X 00000000
Resets (Above)
Register
UDDR9
Bits Name Description
31:8 Reserved for future use.
7:0 DATA Top of endpoint data currently being read.
Register Name: UDDR10
Hex Offset Address: 0 x C800B0C0 Reset Hex Value: 0x00000000
Register
Description:
Universal Serial Bus Device Endpoint 10 Data Register
Access: Write
Bits
31 87 0
(Reserved) (8-Bit Data)
X 00000000
Resets (Above)
Register
UDDR10
Bits Name Description
31:8 Reserved for future use.
7:0 DATA Top of endpoint data currently being loaded.