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Intel
®
IXP42X product line and IXC1100 control plane processors—High-Speed Serial
Interfaces
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
450 Order Number: 252480-006US
The actual FIFO the byte is extracted from is dependent upon the protocol implemented
and the FIFO arrangement. For more details, see the Intel
®
IXP400 Software
Programmer’s Guide.
When the HSS transmit interface processes the third byte (time slot 2), the look-up
table will indicate that the byte to be transmitted is an unassigned cell. Using Intel-
supplied APIs, the Intel XScale
®
Processor can program the HSS interface to transmit
one of three values in an unassigned time slot:
When the HSS transmit interface processes the fourth byte (time slot 3), the look-up
table will indicate that the byte to be transmitted is a 56-K mode cell and is located in
the Voice FIFO. When the transmit interface detects from the transmit look-up table
that the slot to be transmitted is a 56-K mode byte, only seven of the eight bits in a
time slot will be valid. The most-significant bit or the least-significant bit will be invalid.
Using Intel-supplied APIs, the Intel XScale processor can program the invalid bit
location as well as the value to be placed into the invalid bits location when data is
transmitted. The data inserted into the invalid bit location can be programmed to be
logic 0, logic 1, or tristate. For more details, see the Intel
®
IXP400 Software
Programmer’s Guide.
17.3 Configuration of the High-Speed Serial Interface
As shown in the previous sections, a wide variety of interface flexibility can be
implemented over the High-Speed Serial Interface using various configuration
parameters and developing new code on the Network Processor Engine (NPE). For
details on current HSS interface configurations supported, see the Intel
®
IXP400
Software Programmer’s Guide.
The remainder of this section outlines the HSS interface configuration parameters that
can be programmed using Intel-supplied APIs.
There are various programmable functions of the HSS interfaces that have already
been described, such as
• Ability to support 56-K time slots
• Ability to select the location of the invalid bit and —
— The value to be transmitted when transmitting the invalid bit location
— The a value to be sent when transmitting an unassigned time slot
• Ability to classify each time slot using the transmit and receive look-up tables
There are, however, many other programmable features of the HSS interface. They
include the ability to:
• Set the frame length
• Set the sampling edge of the frame-sync and the data independently
• Generate/receive a framing bit
• Source/receive the frame-sync signal
• Source/receive the transmit and receive clocks
• Manipulate the definition of a valid frame-sync signal
• Set an offset for the frame-sync signal
• Source various output clock rates
• All zeros • All ones • High-impedance