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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 425
Ethernet MAC A—Intel
®
IXP42X product line and IXC1100 control plane processors
(assuming bit 1 of Receive Control Register 1 is set to logic 1) and capture the
remaining data. Padded bytes will not be removed from the received packet when bit
1 of Receive Control Register is set to logic 0.
If the packet is less than 64 bytes and there are no padded bytes, the packet is
determined to be a runt frame. The Receive Engine has the capability to discard these
frames or forward the frames to the NPE via the remaining receive logic.
Setting bit 6 of Receive Control Register 1 (RXCTRL1) to logic 1 informs the Receive
Engine to allow the packet to be sent to the NPE. Setting bit 6 of Receive Control
Register 1 (RXCTRL1) to logic 0 informs the Receive Engine to terminate the reception
of the runt packet and purge the runt packet from the rest of the receive logic.
If the length/type is determined to be a type field, the field is looked at for validity.
Invalid frames are purged from the receive logic.
Once the received frame has passed the frame validity checks, the received frame will
be checked for integrity using the Frame-Check Sequence Algorithm called out in the
transmit-frame section. If the frame passes the Frame Check Sequence, the frame will
be forwarded on to the NPE via the remaining receive logic. If the frame fails the Frame
Check Sequence, the frame will be discarded along with purging all of the remaining
receive logic of the frames contents.
Padded bytes will be included in the calculation of the Receive Engine’s Frame Check
Sequence for frames that were transmitted and were smaller than the 64-byte
minimum frame size. A status flag will be sent to the NPE to inform the NPE what to
do with the received frame.
In addition to the above features, the MII receive interface allows some features to be
used for test and debug. The transmit interface can be looped back to the receive
interface by setting bit 4 of Receive Control Register 1 (RXCTRL1) to logic 1. In loop-
back mode, the Receive Engine will receive all of the data sent by the Transmit Engine.
The loop-back feature allows software developers to develop their application code and
test the code before they start dealing with physical interface problems. Setting bit 0 of
Receive Control Register 1(RXCTRL1) to logic 1 enables the Receive Engine. This
feature allows all initialization of the product to occur prior to bring the receive
interface online. Bit 0 of Receive Control Register 2 (RXCTRL2) enables deferral
checking on the receive side. The IXP42X product line and IXC1100 control plane
processors do not use the receive side deferral checking feature.
Bit 0 of Receive Control Register 2 (RXCTRL2) must be set to logic 0 for proper
operation. Failure to do so will result in unpredictable behavior.
Intel recommends that the register values described in this section be manipulated
through Intel-supplied APIs. Failure to use the Intel supplied APIs will result in
unpredictable results.
15.1.6 General Ethernet Coprocessor Configuration
The Ethernet coprocessor contains various other registers that are used to configure
the interface. Some of these registers are included due to the generic nature of the
Ethernet coprocessor. Other registers are added to allow greater flexibility in
configuration of the Ethernet coprocessor.
The Threshold for Internal Clock (THRESH_INTCLK) Register is used to determine the
frequency relationship between the MII interface and the host processor that is used to
control the MII interface. The value in the Threshold for Internal Clock
(THRESH_INTCLK) Register will be manipulated based upon the ratio of
PHY_CLK_SPEED/HOST_CLK_SPEED.