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Intel
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IXP42X product line and IXC1100 control plane processors—Interrupt Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
406 Order Number: 252480-006US
13.5.8 FIQ Highest-Priority Register
§ §
Register INTR_IRQ_ENC_ST
Bits Name Description
31:8 Zero Read as undefined
7:2 IRQ_ENC_ST
Indicates the highest priority pending Maskable interrupt (the interrupt
“number” incremented by 1)
1:0 Zero Zero
Register Name: INTR_FIQ_ENC_ST
Hex Offset Address: 0xC800 301C Reset Hex Value: 0x00000000
Register
Description:
This register returns the “incremented number” of the highest-priority interrupt that is pending for the
FIQ. For example, if interrupt ‘0’ is the highest FIQ pending, the register returns 1.
Note that the encoded number is shifted left by two bits, a software requirement for the value to be
multiplied by 4 before being read.
Access: Read.
31 87 210
(Undefined) FIQ_ENC_ST RES
Register
INTR_FIQ_ENC_ST
Bits Name Description
31:8 Zero Read as undefined
7:2 FIQ_ENC_ST
Indicates the highest-priority, pending FIQ interrupt (the interrupt “number”
incremented by 1)
1:0 Zero Zero