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Intel
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IXP42X product line and IXC1100 control plane processors—JTAG Interface
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
552 Order Number: 252480-006US
20.1.10 Select-IR-Scan State
The Select-IR Scan state is a temporary controller state. The test data registers
selected by the current instruction retain their previous state.
In this state, if JTG_TMS is logic 0 on the rising edge of JTG_TCK, the controller moves
into the Capture-IR state, and a scan sequence for the instruction register is initiated.
If JTG_TMS is logic 1 on the rising edge of JTG_TCK, the controller moves to the Test-
Logic-Reset state.
The instruction does not change in this state.
20.1.11 Capture-IR State
When the controller is in the Capture-IR state, the shift register — implemented for the
instruction register — loads the fixed value 0000001 on the rising edge of JTG_TCK as
defined by the IEEE-1149 specification.
The test data register, selected by the current instruction, retains its previous value
during this state. The instruction does not change in this state.
While in this state, the holding of JTG_TMS at logic 1 on the rising edge of JTG_TCK
causes the controller to enter the Exit1-IR state. If JTG_TMS is held at logic 0 on the
rising edge of JTG_TCK, the controller enters the Shift-IR state.
20.1.12 Shift-IR State
When the controller is in the Shift-IR state, the shift register, contained in the
instruction register, is connected between JTG_TDI and JTG_TDO and shifts data one
bit position nearer to its serial output on each rising edge of JTG_TCK. The shifting also
allows the loading of the next instruction that is to be loaded into the TAP controller.
The value of binary 0000001 loaded during the Capture-IR state will be shifted towards
the JTG_TDO output.
The test data register selected by the current instruction retains its previous value
during this state. The instruction does not change.
If JTG_TMS is logic 1 on the rising edge of JTG_TCK, the controller enters the Exit1-IR
state. If JTG_TMS is logic 0 on the rising edge of JTG_TCK, the controller remains in the
Shift-IR state.
20.1.13 Exit1-IR State
The Exit1-IR state is a temporary state. If JTG_TMS is logic 0 on the rising edge of
JTG_TCK, the controller enters the Update-IR state, which terminates the scanning
process. If JTG_TMS is logic 0 on the rising edge of JTG_TCK, the controller enters the
Pause-IR state.
The test data register selected by the current instruction retains its previous value
during this state.
The instruction does not change and the instruction register retains its state.
20.1.14 Pause-IR State
The Pause-IR state allows the test controller to temporarily halt the shifting of data
through the instruction register. The test data registers selected by the current
instruction retain their previous values during this state.