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Intel
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IXP42X product line and IXC1100 control plane processors—AHB Queue Manager (AQM)
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
560 Order Number: 252480-006US
interface is written into SRAM at the calculated queue address. When the read and
write pointers are equal, the queue is either full or empty as determined by the full or
empty status flags.
When a read request of an empty queue buffer is performed, queue control will return
zeroes in the data field to the AHB interface and will set the Underflow Status Flag.
When a write request of a full queue is performed, queue control will set the Overflow
Status Flag. Underflow and Overflow Status Flags are maintained on queues 0-31 only.
Otherwise for a read request of an empty queue or write request of a full queue, queue
control will not perform any action upon the queue buffer or queue configuration word.
Following the queue access, the appropriate read or write pointer, as indicated by the
type of queue access, is incremented and the queue configuration word, with all other
fields maintained, is written back into SRAM. The queue size will be used in determining
the number of active bits within the allocated 7 bit field for the read and write pointers.
Configurable queue sizes of 16, 32, 64 and 128 directly correspond to read and write
active bit widths of 4, 5, 6, and 7. The unused bits of the read and write pointers will be
zeroed prior to writing the queue configuration word back into SRAM.
One to four Queue Access Register addresses, 0, 4, 8, and 0xC, are allocated per queue
as determined by the queue’s programmed entry size. Thus a queue, with an entry size
set to one word, will support accesses to the first location, 0, and a queue with an entry
size set to two, will support accesses to the first and second locations, 0 and 4. A queue
with an entry size set to four words will support accesses to all four locations. Accesses
to the non-supported locations will not be performed and queue read/write pointers will
be unchanged. A queue, with a programmed entry size of two or four words, requires
the two or four accesses of each queue entry to be performed sequentially beginning
with address 0. Accesses performed out of order will not be performed. Incomplete
accesses (e.g. reading only the first two words of a four word entry) will not update the
pointers. The sequential accesses can be performed via multiple single word accesses
or via a burst access on the AHB. If a Queue burst access of more than four words is
attempted, the AQM will perform the accesses to the first two or four locations, as
determined by the queue’s entry size, and the remainder of the accesses of the burst
will not be performed. The AQM will respond with the OKAY response on the AHB when
the queue accesses aren’t performed. Queue read accesses which are not performed,
will return zeroes in the data field on the AHB.
21.4.2 Queue Status
Status information for the 64 queues is provided in the status registers. Six status flags
will be maintained for each of the queues 0-31, empty, nearly empty, full, nearly full,
underflow, and overflow. Only the four Empty, Nearly Empty, Nearly Full, and Full
Status Flags are provided for queues 32-63. The status flags will be read/write
accessible via the AHB, although the arrangement of flags differs between queues 0-31
and 32-63. The Flag Bus will communicate status for queues 0-31 to the NPEs, while
two interrupts will provide status interrupting capability for the Intel XScale processor.
The following sections outline the queue status requirements.
21.4.2.1 Status Update
Following any updates for a queue access, the read and write pointers will be used in
determination of status flag settings for the accessed queue. When the queue entry
size is set to 1, status flags are updated following every queue access. If the queues
are set for multi-word entry sizes, 2 or 4, the status flags will be updated following the
queue access, that completely fills or empties a queue entry. If the read and write
pointers are equal and the last access to the queue was a read, then the queue is
empty. If the read and write pointers are equal and the last access was a write, then
the queue is full. The nearly empty and nearly full configurable watermarks are used in
determining the settings for the NE and NF Status flags. These watermarks can be set
to 0, 1, 2, 4, 8, 16, 32, or 64 entries. If the number of completely empty entries is less