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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 451
High-Speed Serial Interfaces—Intel
®
IXP42X product line and IXC1100 control plane
processors
• Loop back the transmit to receive interface internally.
The following discussion briefly describes these features. For more detail on
manipulating these settings, see the Intel
®
IXP400 Software Programmer’s Guide.
The frame length can be set as a variable function with the maximum frame length
being 1,024 bits. The size of the frame length is tightly coupled with the protocol that is
implemented by the Network Processor Engine. For the maximum/minimum frame
length value and the protocols that are implemented, see the Intel
®
IXP400 Software
Programmer’s Guide.
The High-Speed Serial Interfaces provides the capability to sample data on the rising or
falling edge of the receive clock. The same ability exists for the sampling of the frame-
sync signal when the frame-sync signal is configured as an input. The HSS interfaces
provides the capability to source data and the frame-sync signal on the rising and
falling edge of the transmit clock assuming that the frame-sync signal is being sourced
by the IXP42X product line and IXC1100 control plane processors.
If the transmit frame-sync signal is being generated from an external source and the
IXP42X product line and IXC1100 control plane processors is sampling this signal, the
HSS interface has the capability to sample this data on the rising or falling edge. The
data and frame-sync edge generation/detection logic can be set independently for both
receive and transmit directions.
For example:
• The receive data may be sampled on the rising (or falling) edge of the receive clock
• The receive frame-sync signal may be sampled on the rising (or falling) edge of the
receive clock
• The transmit data may be sourced on the rising (or falling) edge of the transmit
clock
• The transmit frame sync may be generated on the falling (or rising) edge of the
transmit clock when the IXP42X product line and IXC1100 control plane processors
sources the frame-sync signal
• The transmit frame sync may be sampled on the falling (or rising) edge of the
transmit clock when the IXP42X product line and IXC1100 control plane processors
received the frame-sync signal from an external source
The ability to select the clock edge for sourcing or receiving these signals allows for the
maximum flexibility when attempting to meet setup/hold timing between the devices
connected. Another point to note is that the receive frame-sync pulse can be
programmed to be driven or received by the IXP42X product line and IXC1100 control
plane processors. The programmable selection of the data and frame-sync signals are
implemented for independently for both HSS interfaces.
To allow the maximum flexibility in a users design, the IXP42X product line and
IXC1100 control plane processors provide the ability for the clocks to be generated by
the HSS interface or the clocks to be sampled from an external source by the HSS
interface. The direction selected for the clocks can be on an individual basis.
The transmit clock can be defined as an input and the receive clock can be configured
as an output. The settings are available for each HSS interface. When the clocks are
configured as an output, the clock speeds that can be configured are:
• 512 KHz • 1.536 MHz • 1.544 MHz
• 2.048 MHz • 4.096 MHz • 8.192 MHz