Filter
Top Products
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 249
PCI Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
3. Wait 1ms to satisfy minimum reset assertion time of the PCI specification.
4. Configure the PCI clock GPIO for the proper PCI bus frequency (defined in the
section GPIO).
5. Enable the PCI clock GPIO to drive the PCI clock
6. Wait 100 µs to satisfy the “minimum reset assertion time from clock stable”
requirement of the PCI specification.
7. Set the PCI reset GPIO output to drive a 1.
This releases the PCI bus.
Note: The PCI reset can be asserted and de-asserted asynchronously with respect to the PCI
clock. It is also important to note the PCI reset signal can not be the same signal as the
RESET_IN_N signal going to the IXP42X product line and IXC1100 control plane
processors due to PCI reset timing and PCI initialization requirements.
6.13 PCI RCOMP Circuitry
The PCI RCOMP circuitry dynamically compensates for variations in operating
conditions due to process, temperature and voltage. These variations are measured
through a resistive mechanism in a special I/O Pad and evaluated in the associated
compensation circuitry. Adjustments are made to the drive strength of the buffers for
the PCI interface ensuring error free operation over the entire range of operating
conditions.
The RCOMP circuitry requires an external reference resistor that models the load the
PCI pads will see in the board environment. For specific RCOMP pin requirements, see
the Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane
Processor Datasheet (252479). The circuitry adjusts the PCI pads' current sourcing
strength by comparing the voltage of the output buffer driven through the external
reference resistor with an internally generated 60% threshold voltage. The circuitry
adjusts the PCI pads' current sinking strength by comparing the output buffer voltage
with an internally generated 40% threshold voltage. Once drive strengths are
determined for the 60% and 40% thresholds a multiplier is applied to the drive
strengths to provide for a margin above and below the 60% and 40% thresholds,
respectively.
6.14 Register Descriptions
6.14.1 PCI Configuration Registers
Table 103 lists the registers comprising the configuration registers as defined in the PCI
Local Bus Specification, Rev. 2.2. They are accessible from the PCI bus using
configuration read and write transactions and from the Intel XScale processor by
accessing the PCI Controller CSR-based PCI Configuration register port. Access to these
registers are described in “Initializing the PCI Controller Configuration Registers” on
page 222
Table 103. PCI Configuration Register Map (Sheet 1 of 2)
Offset Register Name Description
0x00 PCI_DIDVID Device ID/Vendor ID
0x04 PCI_SRCR Status Register/Control Register
0x08 PCI_CCRID Class Code/Revision ID
0x0C PCI_BHLC BIST/Header Type/Latency Timer/Cache Line
0x10 PCI_BAR0 Base Address 0