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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 471
Universal Serial Bus (USB) v1.1 Device Controller—Intel
®
IXP42X product line and IXC1100
control plane processors
By decoding the polarity of the UDC+ and UDC- pins and using differential data, four
distinct states are represented. Two of the four states are used to represent data. A 1
indicates that UDC+ is high and UDC- is low. A 0 indicates that UDC+ is low and UDC-
is high. The two remaining states and pairings of the four encodings are further
decoded to represent the current state of the USB.
Table 161 shows how differential signalling represents eight different bus states.
USB Hosts and USB hubs have pull-down resistors on both the D+ and D- lines. When
a device is not attached to the cable, the pull-down resistors cause D+ and D- to be
pulled down below the single-ended low threshold of the USB host or USB hub. This
creates a state called single-ended zero (SE0). A disconnect is detected by the USB
host when an SE0 persists for more than 2.5 µs (30-bit times). When the UDC is
connected to the USB cable, the pull-up resistor on the UDC+ pin causes D+ to be
pulled above the single-ended high threshold level. After 2.5 µs elapse, the USB host
detects a connect.
After the USB Host detects a Connect, the bus is in the idle state because UDC+ is high
and UDC- is low. The bus transitions from the Idle state to the Resume state (a 1-to-0
transition) to signal the Start of Packet (SOP). Each USB packet begins with a Sync field
that starts with the 1-to-0 transition.
After the packet data is transferred, the bus signals the End of Packet (EOP) state by
pulling both UDC+ and UDC- low for 2 bit times, followed by an Idle state for 1 bit time.
If the idle persists for more than 3 ms, the UDC enters Suspend state. The USB Host
can awaken the UDC from the Suspend state by signalling a reset or by switching the
bus to the resume state via normal bus activity. Under normal operating conditions, the
USB host periodically signals an Start of Frame (SOF) to ensure that devices do not
enter the suspend state.
18.3.2 Bit Encoding
USB uses non-return to zero inverted (NRZI) to encode individual bits. Both the clock
and the data are encoded and transmitted within the same signal. Instead of
representing data by controlling the state of the signal, transitions are used. A 0 is
represented by a transition, and a 1 is represented by no transition (this produces the
data).
Table 161. USB States
Bus State UDC+/UDC- Pin Levels
Idle UDC+ high, UDC- low (same as a 1).
Suspend Idle state for more than 3 ms.
Resume UDC+ low, UDC- high (same as a 0).
Start of Packet Transition from idle to resume.
End of Packet UDC+ AND UDC- low for 2-bit times followed by an idle for 1-bit time.
Disconnect
UDC+ AND UDC- below single-ended low threshold for more than 2.5 µs.
(Disconnect is the static bus condition that results when no device is plugged into a hub
port.)
Connect UDC+ OR UDC- high for more than 2.5 µs.
Reset
UDC+ AND UDC- low for more than 2.5 µs. (Reset is driven by the USB host controller
and sensed by a device controller.)