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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 85
Intel XScale
®
Processor—Intel
®
IXP42X product line and IXC1100 control plane processors
3.5.1.15 Register 14: Breakpoint Registers
The Intel XScale processor contains two instruction breakpoint address registers
(IBCR0 and IBCR1), one data breakpoint address register (DBR0), one configurable
data mask/address register (DBR1), and one data breakpoint control register (DBCON).
The Intel XScale processor also supports a 256-entry, trace buffer that records program
execution information. The registers to control the trace buffer are located in CP14.
Refer to “Software Debug” on page 88 for more information on these features of the
Intel XScale processor.
3.5.1.16 Register 15: Coprocessor Access Register
This register is selected when opcode_2 = 0 and CRm = 1.
This register controls access rights to all the coprocessors in the system except for
CP15 and CP14. Both CP15 and CP14 can only be accessed in privilege mode. This
register is accessed with an MCR or MRC with the CRm field set to 1.
This register controls access to CP0, atypical use for this register is for an operating
system to control resource sharing among applications. Initially, all applications are
denied access to shared resources by clearing the appropriate coprocessor bit in the
Coprocessor Access Register. An application may request the use of a shared resource
(e.g., the accumulator in CP0) by issuing an access to the resource, which will result in
an undefined exception. The operating system may grant access to this coprocessor by
setting the appropriate bit in the Coprocessor Access Register and return to the
application where the access is retried.
Sharing resources among different applications requires a state saving mechanism.
Two possibilities are:
• The operating system, during a context switch, could save the state of the
coprocessor if the last executing process had access rights to the coprocessor.
• The operating system, during a request for access, saves off the old coprocessor
state and saves it with last process to have access to it.
Under both scenarios, the OS needs to restore state when a request for access is made.
This means the OS has to maintain a list of what processes are modifying CP0 and their
associated state.
Table 25. Accessing the Debug Registers
Function opcode_2 CRm Instruction
Access Instruction Breakpoint
Control Register 0 (IBCR0)
0b000 0b1000
MRC p15, 0, Rd, c14, c8, 0 ; read
MCR p15, 0, Rd, c14, c8, 0 ; write
Access Instruction Breakpoint
Control Register 1(IBCR1)
0b000 0b1001
MRC p15, 0, Rd, c14, c9, 0 ; read
MCR p15, 0, Rd, c14, c9, 0 ; write
Access Data Breakpoint Address
Register (DBR0)
0b000 0b0000
MRC p15, 0, Rd, c14, c0, 0 ; read
MCR p15, 0, Rd, c14, c0, 0 ; write
Access Data Mask/Address
Register (DBR1)
0b000 0b0011
MRC p15, 0, Rd, c14, c3, 0 ; read
MCR p15, 0, Rd, c14, c3, 0 ; write
Access Data Breakpoint Control
Register (DBCON)
0b000 0b0100
MRC p15, 0, Rd, c14, c4, 0 ; read
MCR p15, 0, Rd, c14, c4, 0 ; write