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Intel
®
IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB)
v1.1 Device Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
484 Order Number: 252480-006US
The status stage for all other USB Standard Commands that do not have a data stage,
such as SET_ADDRESS, SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE, and
CLEAR_FEATURE, is handled by the UDC and the software must not set IPR.
18.5.2.3 Flush Tx FIFO (FTF)
The Flush Tx FIFO bit triggers the reset of the endpoint 0 transmit FIFO. It is set when
software writing a 1 or when the UDC receives an OUT packet from the host on
endpoint 0. This bit always reads back a 0 value.
18.5.2.4 Device Remote Wake-Up Feature (DRWF)
The host indicates the state of the device remote wake-up feature by sending a Set
Feature command or a Clear Function command. The UDC decodes the command sent
by the host and sets this bit to a 1 if the feature is enabled and a 0 if the feature is
disabled.
This bit is read-only.
18.5.2.5 Sent Stall (SST)
The sent stall bit is set by the UDC when FST successfully forces a software-induced
STALL on the USB bus. This bit is not set if the UDC detects a protocol violation from
the host when a STALL handshake is returned automatically. In this event, there is no
intervention by the Intel XScale
®
processor and the UDC clears the STALL status before
the host sends the next SETUP command.
When the UDC sets this bit, the transmit FIFO is flushed. The Intel XScale
®
processor
writes a 1 to this bit to clear it.
18.5.2.6 Force Stall (FST)
The force stall bit can be set by the Intel XScale
®
processor to force the UDC to issue a
STALL handshake. The UDC issues a STALL handshake for the current setup control
transfer and the bit is cleared by the UDC because endpoint 0 can not remain in a
stalled condition.
18.5.2.7 Receive FIFO Not Empty (RNE)
The receive FIFO not empty bit indicates that the receive FIFO contains unread data. To
determine if the FIFO has data in it, this bit must be read when the UDCCS0[OPR] bit is
set. The receive FIFO must continue to be read until this bit clears or the data will be
lost.
If UDCCS0[RNE] is not set when an interrupt generated by UDCCS0[OPR] is initially
serviced, it indicates that a zero-length OUT packet was received.
18.5.2.8 Setup Active (SA)
The Setup Active bit indicates that the current packet in the FIFO is part of a USB setup
command. This bit generates an interrupt and becomes active at the same time as
UDCCS0[OPR]. Software must clear this bit by writing a 1 to it. Both UDCS0[OPR] and
UDCCS0[SA] must be cleared.