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Intel
®
IXP42X product line and IXC1100 control plane processors—Intel XScale
®
Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
162 Order Number: 252480-006US
the code fragment, there is a result dependency between the UMLAL instruction and
the SUB instruction. In Table 77, UMLAL starts to issue at cycle 0 and the SUB issues
at cycle 5. thus the Result Latency is five.
3.9.4.2 Branch Instruction Timings
(
3.9.4.3 Data Processing Instruction Timings
Table 77. Latency Example
Cycle Issue Executing
0 umlal (1st cycle) --
1 umlal (2nd cycle) umlal
2add umlal
3 sub (stalled) umlal & add
4 sub (stalled) umlal
5sub umlal
6mov sub
7-- mov
Table 78. Branch Instruction Timings (Those Predicted by the BTB)
Mnemonic
Minimum Issue Latency When
Correctly Predicted by the BTB
Minimum Issue Latency with Branch
Misprediction
B1 5
BL 1 5
Table 79. Branch Instruction Timings (Those not Predicted by the BTB)
Mnemonic
Minimum Issue Latency
When the Branch is not Taken
Minimum Issue Latency
When the Branch is Taken
BLX(1) N/A 5
BLX(2) 1 5
BX 1 5
Data Processing Instruction with
PC as the destination
Same as Table 80 4 + numbers in Table 80
LDR PC,<> 2 8
LDM with PC in register list 3 + numreg
*
10 + max (0, numreg-3)
Note: numreg is the number of registers in the register list including the PC.
Table 80. Data Processing Instruction Timings (Sheet 1 of 2)
Mnemonic
<shifter operand> is NOT a Shift/
Rotate by Register
<shifter operand> is a Shift/Rotate
by Register OR
<shifter operand> is RRX
Minimum Issue
Latency
Minimum Result
Latency
*
Minimum Issue
Latency
Minimum Result
Latency
*
ADC1122
ADD1122
AND1122
BIC1122
Note: If the next instruction needs to use the result of the data processing for a shift by immediate or as Rn
in a QDADD or QDSUB, one extra cycle of result latency is added to the number listed.