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Intel
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IXP42X product line and IXC1100 control plane processors—Intel XScale
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Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
82 Order Number: 252480-006US
The line-allocate command allocates a tag into the data cache specified by bits [31:5]
of Rd. If a valid dirty line (with a different MVA) already exists at this location it will be
evicted. The 32 bytes of data associated with the newly allocated line are not initialized
and therefore will generate unpredictable results if read.
Line allocate command may be used for cleaning the entire data cache on a context
switch and also when reconfiguring portions of the data cache as data RAM. In both
cases, Rd is a virtual address that maps to some non-existent physical memory. When
creating data RAM, software must initialize the data RAM before read accesses can
occur. Specific uses of these commands can be found in Chapter 3.0, “Data Cache”.
Other items to note about the line-allocate command are:
• It forces all pending memory operations to complete.
• Bits [31:5] of Rd is used to specific the virtual address of the line to be allocated
into the data cache.
• If the targeted cache line is already resident, this command has no effect.
• The command cannot be used to allocate a line in the mini Data Cache.
• The newly allocated line is not marked as “dirty” so it will never get evicted.
However, if a valid store is made to that line it will be marked as “dirty” and will get
written back to external memory if another line is allocated to the same cache
location. This eviction will produce unpredictable results.
To avoid this situation, the line-allocate operation should only be used if one of the
following can be guaranteed:
— The virtual address associated with this command is not one that will be
generated during normal program execution. This is the case when line-allocate
is used to clean/invalidate the entire cache.
— The line-allocate operation is used only on a cache region destined to be
locked. When the region is unlocked, it must be invalidated before making
another data access.
3.5.1.9 Register 8: TLB Operations
Disabling/enabling the MMU has no effect on the contents of either TLB: valid entries
stay valid, locked items remain locked. All operations defined in Table 19 work
regardless of whether the TLB is enabled or disabled.
This register should be accessed as write-only. Reads from this register, as with an
MRC, have an undefined effect.
3.5.1.10 Register 9: Cache Lock Down
Register 9 is used for locking down entries into the instruction cache and data cache.
(The protocol for locking down entries can be found in Chapter 3.0, “Data Cache”.)
Table 19. TLB Functions
Function opcode_2 CRm Data Instruction
Invalidate I&D TLB 0b000 0b0111 Ignored MCR p15, 0, Rd, c8, c7, 0
Invalidate I TLB 0b000 0b0101 Ignored MCR p15, 0, Rd, c8, c5, 0
Invalidate I TLB entry 0b001 0b0101 MVA MCR p15, 0, Rd, c8, c5, 1
Invalidate D TLB 0b000 0b0110 Ignored MCR p15, 0, Rd, c8, c6, 0
Invalidate D TLB entry 0b001 0b0110 MVA MCR p15, 0, Rd, c8, c6, 1