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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 507
Universal Serial Bus (USB) v1.1 Device Controller—Intel
®
IXP42X product line and IXC1100
control plane processors
The UDCCS11[SST] bit is set when the STALL state is actually entered, but this may be
delayed if the UDC is active when the UDCCS11[FST] bit is set. The UDCCS11[FST] bit
is automatically cleared when the UDCCS11[SST] bit is set.
To ensure that no data is transmitted after the Clear Feature command is sent and the
host resumes IN requests, software must clear the transmit FIFO by setting the
UDCCS11[FTF] bit.
18.5.13.7 Bit 6 Reserved
Bit 6 is reserved for future use.
18.5.13.8 Transmit Short Packet (TSP)
The software uses the transmit short packet bit to indicate that the last byte of a data
transfer to the FIFO has occurred. This indicates to the UDC that a short packet or zero-
sized packet is ready to transmit.
Software must not set this bit if a 64-byte packet is to be transmitted. When the data
packet is successful transmitted, the UDC clears this bit.
Register Name: UDCCS11
Hex Offset Address: 0 x C800B03C Reset Hex Value: 0 x 00000001
Register
Description:
Universal Serial Bus Device Controller Endpoint 11 Control and Status Register
Access: Read/Write
Bits
31 876543210
(Reserved)
TSP
(Rsvd)
FST
SST
TUR
FTF
TPC
TFS
X 00000001
Resets (Above)
Register
UDCCS11 (Sheet 1 of 2)
Bits Name Description
31:8 Reserved for future use.
7TSP
Transmit short packet (read/write 1 to set).
1 = Short packet ready for transmission.
6 (Reserved). Always reads 0.
5FST
Force STALL (read/write).
1 = Issue STALL handshakes to IN tokens.
4 SST
Sent STALL (read/write 1 to clear).
1 = STALL handshake was sent.
3TUR
Transmit FIFO underrun (read/write 1 to clear).
1 = Transmit FIFO experienced an underrun.