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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 461
High-Speed Serial Interfaces—Intel
®
IXP42X product line and IXC1100 control plane
processors
• Frame sync simultaneous with first data nibble - set TX frame offset and RX frame
offset due to HSS logic, different values due to external device can be
accommodated.
• Select use of input/output TX/RX frame syncs.
• Select use of input/output clock, and clock speed.
• Select negative/positive clock for generating/sampling frame in transmit/receive.
• Select negative/positive clock for generating/sampling data in transmit/receive.
• Frame sync active level (high/low).
• MSb/LSb-first ordering for transmit and receive.
• Data polarity, maintain or invert.
• Select not to use FBit in the frame.
• Select level for idle timeslots on transmit and unused bit in 56k timeslots.
• Select buffer size.
• Set interlace mode (byte/frame)
• Set lookup tables.
The HSS clocks are capable of running at 1.544MHz, 2,048MHz, 4.096MHz and 8.192
MHz for MVIP mode.
The following three sections describe the three ways in which the MVIP protocol can
operate. The TX and RX are not explicitly described in these sections, as the RX side of
the protocol is identical to the TX side of the protocol.
17.6.3.1 MVIP using 2.048Mbps Backplane
The clock rate for this form of T1 is 2.048Mbps as opposed to the usual T1 rate of 1.544
Mbps. The data rate remains at 1.544Mbps, meaning that certain timeslots within the
frame carry no data and thus are discarded by the HSS interface, as defined by
unassigned timeslots configured by the look up tables. This is illustrated in Figure 90