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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 521
Universal Serial Bus (USB) v1.1 Device Controller—Intel
®
IXP42X product line and IXC1100
control plane processors
18.5.21 UDC Status/Interrupt Register 1 (USIR1)
18.5.21.1 Endpoint 8 Interrupt Request (IR8)
The interrupt request bit is set if the IM8 bit in the UDC Interrupt Control Register is
cleared and the IN packet complete (TPC) or Transmit Underrun (TUR) in UDC Endpoint
8 Control/Status Register is set.
The IR8 bit is cleared by writing a 1 to it.
18.5.21.2 Endpoint 9 Interrupt Request (IR9)
The interrupt request bit is set if the IM9 bit in the UDC Interrupt Control Register is
cleared and the OUT packet ready (RPC) or receiver overflow (ROF) in the UDC
Endpoint 9 Control/Status Register or the Isochronous Error Endpoint 9 (IPE9) in the
UFNHR are set.
The IR9 bit is cleared by writing a 1 to it.
18.5.21.3 Endpoint 10 Interrupt Request (IR10)
The interrupt request bit is set if the IM10 bit in the UDC Interrupt Control Register is
cleared and the IN packet complete (TPC) or in UDC endpoint 10 control/status register
is set.
The IR10 bit is cleared by writing a 1 to it.
18.5.21.4 Endpoint 11 Interrupt Request (IR11)
The interrupt request bit is set if the IM11 bit in the UDC Interrupt Control Register is
cleared and the IN packet complete (TPC) in UDC Endpoint 11 Control/Status Register
is set.
The IR11 bit is cleared by writing a 1 to it.
18.5.21.5 Endpoint 12 Interrupt Request (IR12)
The interrupt request bit is set if the IM12 bit in the UDC Interrupt Control Register is
cleared and the OUT packet ready bit (RPC) in the UDC endpoint 12 control/status
register is set.
The IR12 bit is cleared by writing a 1 to it.
18.5.21.6 Endpoint 13 Interrupt Request (IR13)
The interrupt request bit is set if the IM13 bit in the UDC Interrupt Control Register is
cleared and the IN packet complete (TPC) or Transmit Underrun (TUR) in UDC Endpoint
13 Control/Status Register is set.
The IR13 bit is cleared by writing a 1 to it.
18.5.21.7 Endpoint 14 Interrupt Request (IR14)
The interrupt request bit is set if the IM14 bit in the UDC Interrupt Control Register is
cleared and the OUT packet ready (RPC) or receiver overflow (ROF) in the UDC
Endpoint 14 Control/Status Register or the Isochronous Error Endpoint 14 (IPE14) in
the UFNHR are set.
The IR14 bit is cleared by writing a 1 to it.