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Intel
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IXP42X product line and IXC1100 control plane processors—PCI Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
216 Order Number: 252480-006US
It is also noteworthy to mention that the PCI Controller does not interpret or
manipulate the contents of the Non-Pre-fetch Registers. The address, command, byte
enables, and write data are passed to the PCI bus as-is. For example, I/O read and I/O
write requests must be set-up such that the byte-enables are consistent with the 2
LSBs of the address in accordance with the PCI local-bus specification.
Implication: If an external PCI device has non-prefetch memory and requires either a 16-bit or 8-bit
read, there is a possibility that the device will not respond correctly to the IXP42X
product line and IXC1100 control plane processors’ memory reads. This is because the
IXP42X product line and IXC1100 control plane processors always perform a 32-bit
read to the non-prefetch memory region specified in register PCI_NP_AD.
The 8-bit or 16-bit external device should respond with a “target abort,” as per the PCI
2.2 specification, if a 32-bit read is performed to its non-prefetch memory and it
requires a 16-bit or 8-bit read.
The IXP42X product line and IXC1100 control plane processors will drive all the byte
enables asserted during all memory cycle reads of the external PCI device, no matter
what the PCI_NP_CBE register contains in the byte enable bits.
To read non-prefetch memory sub-DWORDS (8-bit or 16-bit), use I/O reads. If it is
necessary to use memory cycle reads of sub-DWORDS, a hardware resolution may be
required. Contact your Intel field application engineer if you require a hardware
resolution.
6.1.1 Example: Generating a PCI Configuration Write and Read
This example examines the initializing of the Base Address Register.
1. Assume a PCI device has been located and now the Base Address Register
configuration of this PCI device is going to be initialized. The first step is to write all
logic 1s to the PCI Base Address Registers.
Base Address Register 0 will be located at hexadecimal offset of 0x10 when the
ID_SEL of this device is active and the access is a PCI Bus Configuration Cycle. The
intent of this exercise is to initialize this Base Address Register.
2. Write a hexadecimal value of 0x00010010 to the PCI Non-Pre-fetch Access Address
(PCI_NP_AD) Register.
This value will allow a write to a Type 0 PCI configuration space address location
0x10. Notice also that address bit 16 is set to logic 1. This bit is set, assuming that
ID_SEL for a given device on the local segment is selected using address bit 16.
This value chosen for PCI_NP_AD follows the convention outlined in
Figure 33,
“Type 0 Configuration Address Phase” on page 214
.
3. Write a hexadecimal value of 0x0000000B to the PCI Non-Pre-fetch Access
Command/Byte Enables (PCI_NP_CBE) Register.
Bits 7:4 of this register specify the byte enables for the data transfer. The selection
of all bits to logic 0 signifies that all bytes are to be written. Bits 3:0 of this register
specify the PCI Command Type to be used for the data transfer. A logic value of
1011b signifies that a Configuration Write Cycle is being requested.
4. Write a hexadecimal value of 0xFFFFFFFF to the PCI Non-Pre-fetch Access Write
Data (PCI_NP_WDATA) Register.
This write to the Configuration and Status Registers will cause a PCI Configuration
Write Cycle with all byte-enables active to be initiated on the PCI bus.
5. Base Address Register 0 has been written with all logic 1s. However, only some of
these bits will be set to logic 1.
Logic 1s will only be written to the bits corresponding to a given address space
defined for the PCI device. For instance, assume that the PCI device being
configured requires a 64-Mbyte address space for Base Address Register 0 used for