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Intel
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IXP42X product line and IXC1100 control plane processors—Intel XScale
®
Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
136 Order Number: 252480-006US
3.7.2.4 Interrupt Enable Register
(INTEN)
Each counter can generate an interrupt request when it overflows. INTEN enables
interrupt requesting for each counter.
3.7.2.5 Overflow Flag Status Register
(FLAG)
FLAG identifies which counter has overflowed and also indicates an interrupt has been
requested if the overflowing counter’s corresponding interrupt enable bit (contained
within INTEN) is asserted. An overflow is cleared by writing a ‘1’ to the overflow bit.
Table 57. Interrupt Enable Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P
3
P
2
P
1
P
0
C
reset value: [4:0] = 0b00000, others unpredictable
Bits Access Description
31:5 Read-unpredictable / Write-as-0 Reserved
4Read / Write
PMN3 Interrupt Enable (P3) -
0 = disable interrupt
1 = enable interrupt
3Read / Write
PMN2 Interrupt Enable (P2) -
0 = disable interrupt
1 = enable interrupt
2Read / Write
PMN1 Interrupt Enable (P1) -
0 = disable interrupt
1 = enable interrupt
1Read / Write
PMN0 Interrupt Enable (P0) -
0 = disable interrupt
1 = enable interrupt
0Read / Write
CCNT Interrupt Enable (C) -
0 = disable interrupt
1 = enable interrupt