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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 449
High-Speed Serial Interfaces—Intel
®
IXP42X product line and IXC1100 control plane
processors
These buffers also behave in a ping-pong fashion, so the NPE will read two 32-bit words
at a time for processing. The location that each received byte is placed into these FIFOs
is a function of a user programmable look-up table (LUT) and the protocol that is being
implemented.
The look-up table will characterize each received byte as one of four types:
This characterization will be assigned on a time-slot basis using Intel-supplied APIs. For
example, time slot 0 may be defined as a voice cell, time slot 1 as an HDLC wrapped
packet, time slot 2 as an undefined time slot, and time slot 3 defined as an 56-K mode
cell.
When the HSS receive interface processes the first byte (time slot 0), the look-up table
will indicate that this received byte is a voice cell and needs to be placed into the Voice
FIFO. Likewise, when the high-speed serial receive interface processes the second byte
(time slot 1), the look-up table will indicate that this received byte is an HDLC cell and
needs to be placed into one of the HDLC FIFOs. The actual FIFO the byte is placed in is
dependent on the protocol implemented and the FIFO arrangement.
For more details, see the Intel
®
IXP400 Software Programmer’s Guide.
When the high-speed serial receive interface processes the third byte (time slot 2), the
look-up table will indicate that this received byte is an unassigned cell and needs to be
discarded. When the high-speed serial receive interface processes the fourth byte (time
slot 3), the look-up table will indicate that this received byte is a 56-K mode cell and
will also be placed into the Voice FIFO.
17.2 High-Speed Serial Interface Transmit Operation
For transmission using the High-Speed Serial Interface, each High-Speed Serial
Interface contains five transmit FIFOs, organized exactly as the receive FIFOs. (For
additional details on the FIFO organization, see Section 17.1, “High-Speed Serial
Interface Receive Operation” on page 448.)
Each transmitted byte is placed into these FIFOs. The data is transmitted using the
High-Speed Serial Interface as a function of a user programmable look-up table (LUT)
and the protocol that is being implemented.
The look-up table will characterize each byte to be transmitted as one of four types
This characterization will be assigned on a time-slot basis using Intel-supplied APIs.
Assume the same example as before, time slot 0 is be defined as a voice cell, time slot
1 is be defined as an HDLC wrapped packet, time slot 2 is be defined as an undefined
time slot, and time slot 3 is be defined as an 56-K mode cell.
When the HSS transmit interface is ready to process the first byte (time slot 0), the
look-up table will indicate that the byte to be transmitted is a voice cell and needs to be
extracted from the Voice FIFO and placed onto the HSS interface. Likewise, when the
HSS transmit interface is ready to process the second byte (time slot 1), the look-up
table will indicate that the byte to be transmitted is an HDLC cell and needs to be
extracted from one of the HDLC FIFOs and placed onto the HSS interface.
•Unassigned •HDLC
•Voice •56-K mode
•Unassigned •HDLC
•Voice •56-K mode