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Intel
®
IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB)
v1.1 Device Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
512 Order Number: 252480-006US
18.5.16 UDC Endpoint 14 Control/Status Register (UDCCS14)
The UDC Endpoint 14 Control/Status Register contains six bits that are used to operate
endpoint 14, an Isochronous OUT endpoint.
18.5.16.1 Receive FIFO Service (RFS)
The receive FIFO service bit is set if the receive FIFO has one complete data packet in it
and the packet has been error checked by the UDC. A complete packet may be
256 bytes, a short packet, or a zero packet.
UDCCS14[RFS] is not cleared until all data is read from both buffers.
18.5.16.2 Receive Packet Complete (RPC)
The receive packet complete bit gets set by the UDC when an OUT packet is received.
When this bit is set, the IR14 bit in the appropriate UDC status/interrupt register is set
if receive interrupts are enabled. This bit can be used to validate the other status/error
bits in the endpoint 14 control/status register.
The UDCCS14[RPC] bit is cleared by writing a 1 to it.
18.5.16.3 Receive Overflow (ROF)
The receive overflow bit generates an interrupt on IR14 in the appropriate UDC status/
interrupt register to alert the software that Isochronous data packets are being
dropped because neither FIFO buffer has room for them.
This bit is cleared by writing a 1 to it.
18.5.16.4 Bit 3 Reserved
Bit 3 is reserved for future use.
18.5.16.5 Bit 4 Reserved
Bit 4 is reserved for future use.
18.5.16.6 Bit 5 Reserved
Bit 5 is reserved for future use.
3TUR
Transmit FIFO underrun (read/write 1 to clear).
1 = Transmit FIFO experienced an underrun.
2FTF
Flush Tx FIFO (always read 0/ write a 1 to set).
1 = Flush Contents of TX FIFO.
1TPC
Transmit packet complete (read/write 1 to clear).
0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.
0TFS
Transmit FIFO service (read-only).
0 = Transmit FIFO has no room for new data.
1 = Transmit FIFO has room for at least one complete data packet.
Register
UDCCS13 (Sheet 2 of 2)
Bits Name Description