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Intel
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IXP42X product line and IXC1100 control plane processors—Intel XScale
®
Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
94 Order Number: 252480-006US
• CPSR[5] = 0
•CPSR[6] = 1
•CPSR[7] = 1
•PC = 0x0
Note: When the vector table is relocated (CP15 Control Register[13] = 1), the debug vector is
relocated to 0xffff0000.
Following a debug exception, the processor switches to debug mode and enters SDS,
which allows the following special functionality:
• All events are disabled. SWI or undefined instructions have unpredictable results.
The processor ignores pre-fetch aborts, FIQ and IRQ (SDS disables FIQ and IRQ
regardless of the enable values in the CPSR). The processor reports data aborts
detected during SDS by setting the Sticky Abort bit in the DCSR, but does not
generate an exception (processor also sets up FSR and FAR as it normally would for
a data abort).
• Normally, during halt mode, software cannot write the hardware breakpoint
registers or the DCSR. However, during the SDS, software has write access to the
breakpoint registers (see “HW Breakpoint Resources” on page 95) and the DCSR
(see Table 33, “Debug Control and Status Register (DCSR)” on page 90).
• The IMMU is disabled. In halt mode, since the debug handler would typically be
downloaded directly into the IC, it would not be appropriate to do TLB accesses or
translation walks, since there may not be any external memory or if there is, the
translation table or TLB may not contain a valid mapping for the debug handler
code. To avoid these problems, the processor internally disables the IMMU during
SDS.
• The PID is disabled for instruction fetches. This prevents fetches of the debug
handler code from being remapped to a different address than where the code was
downloaded.
The SDS remains in effect regardless of the processor mode. This allows the debug
handler to switch to other modes, maintaining SDS functionality. Entering user mode
may cause unpredictable behavior. The processor exits SDS following a CPSR restore
operation.
When exiting, the debug handler should use:
This restores CPSR, turns off all of SDS functionality, and branches to the target
instruction.
3.6.5.2 Monitor Mode
In monitor mode, the processor handles debug exceptions like normal ARM exceptions.
If debug functionality is enabled (DCSR[31] = 1) and the processor is in Monitor mode,
debug exceptions cause either a data abort or a pre-fetch abort.
The following debug exceptions cause data aborts:
• Data breakpoint
• External debug break
• Trace-buffer full break
The following debug exceptions cause pre-fetch aborts:
subs pc, lr, #4