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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 563
AHB Queue Manager (AQM)—Intel
®
IXP42X product line and IXC1100 control plane processors
21.5.2 Queues 0-31 Status Register 0 - 3
The access to these status registers is read/write, however except for initialization,
diagnostic and test purposes, normal operation to these registers should be read only.
Writing status does not actually change the status, it only writes the shadow register
which contains the status.
21.5.3 Underflow/Overflow Status Register 0 - 1
The access to these status registers is read/write, however except for initialization,
diagnostic and test purposes, normal operation to these registers should be read only.
Writing status does not actually change the status, it only writes the shadow register
which contains the status.
Register Name: QUEACC (0 <= n <=63)
Physical Address:
Queue #n 0x(0000 + 16n
+ 4x)
Reset Hex Value: Not Applicable
Register Description:
Queue #n access register. There are 1-4 addresses (0 <= x <=3), as determined by the
programmed entry size, for requesting read/write accesses to individual queues. No physical
data resides at these addresses.
Access:
Read/Write
3
1
2
4
2
3
1
6
1
5
87 0
Queue Read/Write Data
Register Name: QUELOWSTAT (0 <= n <=3)
Physical Address:
Reg #n 0x(0400 + 4n)
Reset Hex Value: 0x33333333
Register Description:
Queue status register for the queues 0-31.
F/NF/NE/E: ‘1’ – active flag
Access: Read/Write
3
1
1
6
1
5
87 0
Queue(8n+7) Queue(8n+6) Queue(8n+5) Queue(8n+4) Queue(8n+3) Queue(8n+2) Queue(8n+1) Queue(8n)