Filter
Top Products
Intel
®
IXP42X product line and IXC1100 control plane processors—JTAG Interface
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
548 Order Number: 252480-006US
20.0 JTAG Interface
The JTAG signals JTG_TCK, JTG_TRST_N, and JTAG_TDI will be routed to both the Test
Logic Unit (TLU) and the Intel XScale
®
Processor. The Test Logic Unit is a unit that is
provided to implement JTAG functions that are specific the Intel
®
IXP42X Product Line
of Network Processors and IXC1100 Control Plane Processor. The Intel XScale
processor JTAG functionality is consistent among the Intel XScale processor family of
processors.
For additional details on the JTAG functionality supported by the Intel XScale processor,
Section 3.6, “Software Debug” on page 88.
The Test Logic Unit receives the current state of the TAP controller located in the Intel
XScale processor and the current instruction loaded in Intel XScale processor JTAG
Instruction Register. The Test Logic Unit determines if the instruction is for the Intel
XScale processor or the Intel
®
IXP42X product line and IXC1100 control plane
processors Test Logic Unit by decoding the JTAG instruction located in the Intel XScale
processor.
All of the IXP42X product line and IXC1100 control plane processors-specific
instructions — except for HIGH_Z — are intended for one of three data registers in the
TLU (Test Register, Key/Fuse Register, and the Boundary Scan Register) and,
consequently, connect the data register between TDI and TDO.
The Boundary Scan Register is the only register that is accessible to users.
20.1 TAP Controller
A JTAG TAP controller is implemented in the Intel XScale processor. The current state of
the TAP controller is directed to the Test Logic Unit through direct signalling.
The TAP controller is a 16-state, synchronous, finite state machine that changes state
on the rising edge of JTG_TCK. The controller’s next state is controlled by the signal
present on the JTG_TMS input (which only goes to Intel XScale processor, since the
IXP42X product line and IXC1100 control plane processors don’t implement their own
TAP controller).
The TAP controller generates control signals, that — together with JTG_TCK and control
signals decoded from the instruction active in the Intel XScale processor instruction
register — determine the operation of the test circuitry.
For greater detail on the state machine, see IEEE 1149.1a Standard Test Access Port
and Boundary-Scan Architecture.